JPH02301846A - Semiconductor storage element - Google Patents

Abstract

PURPOSE:To easily detect the program state of a nonvolatile memory by reading out the storing information of the memory cell to the outside by selecting the data read out of a cell group in accordance with the storing information of the nonvolatile memory cell. CONSTITUTION:Since reading out data are selected based on the data stored in a nonvolatile memory cell 23, the storing data of the memory cell 23 can be read out equivalently by the selection when cell groups 11 and 12 storing the data corresponding to the storing data of the memory cell 23 are read out at the time of reading out the storing data of the memory cell 23. The transmition route of the read out data is a usual route and no special reading out route, terminal pin, etc., are required for transmitting the storing data of the memory cell 23. Therefore, the state of the program of the nonvolatile memory cell 23 can be detected easily.

Description

[Detailed Description of the Invention] [Summary of the Invention] The present invention relates to a non-volatile semiconductor memory element having a memory section for controlling memory functions, and an object of the present invention is to make it possible to relatively easily detect the programmed state of the non-volatile memory. In a semiconductor memory device that includes a group of cells in which predetermined information is written in a matrix along its specific word line, and also includes nonvolatile memory cells for controlling memory functions, information for controlling memory functions written to the nonvolatile memory cells is , the predetermined information is written in a part of the cell group to be written, and read data from the cell group is selected according to the storage information of the nonvolatile memory cell, and the storage information of the nonvolatile memory cell is externalized. Configure it so that it can be read.

[Industrial application field]

The present invention relates to a nonvolatile semiconductor memory element having a memory section for controlling memory functions.

[Conventional technology]

Recent non-volatile memory devices, especially EEPROM (Elec.
tric-ally Erasable & Prog
ramable Read 0nly Memory)
Now, there is a need for a memory element in which a nonvolatile memory cell separate from the original memory cell array is mounted on a chip, and the element function can be controlled by programming this cell. For example, a technology has been announced that controls the write function according to the programming state of the cell, and allows writing only when writing is permitted, with the aim of preventing erroneous writing and protecting data (such as software write protection). being called).

[Problem to be solved by the invention]

However, since there is no means for externally detecting the programmed state of this memory cell, the only way to know the programmed state is to actually perform writing.

It is an object of the present invention to solve such problems and to make it possible to detect the program state relatively easily.

(Means for Solving the Problems) As shown in FIG.
This cell group of a semiconductor memory element has a cell group 11.12 in which predetermined information, for example, ES, which will be described later, is written along a specific word line, and also has a nonvolatile memory cell 23 in which memory function control information is written. , information corresponding to the memory function control information to be written to the nonvolatile memory cell 23 is written (For example, if writing to the cell matrix 10 is prohibited/enabled, data "' 1 "/" is written to the nonvolatile memory cell 23.
0゛' again in cell group 11. , 12 (the remaining cells in which the BS has been written), information indicating whether writing is prohibited or writable is written.

Furthermore, the memory has a means for selecting a bit line and thus selecting read data, and this selection means is controlled by the data stored in the nonvolatile memory cell 7, and the stored data in the cell groups 11 and 12 corresponding to the stored data is read out. Make it available.

[Effect]

According to this configuration, read data is selected based on the data stored in the non-volatile memory cell 23, so when reading data stored in the non-volatile memory cell, the cell group 11.12 storing data corresponding to the stored data is selected. By reading out the data stored in the nonvolatile memory cell, the above selection can be made isometrically without reading out the data stored in the nonvolatile memory cell.

This read data transmission path is a normal path, and a special read path for storing data stored in nonvolatile memory cells.
No terminal pins are required.

〔Example〕

FIG. 2 shows an embodiment of the present invention. 10 is an array of EEFROM memory cells (cell matrix); 13 is a row decoder for selecting word lines of the cell matrix; 1;
5 is a read column gate for selecting a bit line, 16 is a sense amplifier, 17 is an I10 buffer, and read data is taken out to the outside through a path 10-15-16-17.

RADD is a row address supplied from the outside, which is passed through the row address buffer 14 (each bit of the address and its inverted bit is created in the buffer) and then sent to the row decoder 13.
and is used for word line selection. CADD is a column address, which is inputted to the read column decoder 18 via the read column address buffer 19 to turn on/off the read column gate 15 and select a bit line.

CB, OE, WE are chip enable, output enable, write enable bars, control logic 2
5 to perform CB, OE, and WE control. 24 is a booster circuit, and 20 is a word line booster circuit, which sets the word line to a high potential when writing to a cell matrix. In this memory, the column gates are different for writing and reading, and 22 is the column gate for writing. Column address CADD is input to write column decoder WCD via write column address buffer WCA to select a bit line. Write data is sent to the cell matrix 10 through the I10 buffer 17, write column gate 22, page register and bit line booster circuit 21. This memory allows simultaneous writing of a large number of bits, for example 64 hides, in addition to the usual simultaneous writing of a small number of bits, for example 1 byte. When writing multiple bits at the same time, write only a few bits.
The bits are sent one by one and stored in the page register PR of the circuit 21, and when a large number of bits have been stored, they are written simultaneously.

Also, this type of memory is E S (Electronic).
5iBna-1ure) cell 11.12. For example, a company code, device code, etc. are written in this BS cell. In this example, this is composed of a memory cell group (mask ROM) for one word line, and the ES cell 1,
They are divided into two groups. ESD is a decoder that selects this one word line, and as the output Il of the high voltage detection buffer 29, the row address buffer 14 and the row decoder 1
3 is enabled and the normal decoder section of the cell matrix 10 is selected, or the row address buffer 14 is disabled and ES is selected.
D is enabled and the ES cell section is selected.

Reference numeral 23 denotes a storage section for function control, which in this example is a nonvolatile memory cell for software protection. Writing to the memory cells 23 is from Rough 1 to Wear 8! control by logic 26. If it is only write-protected/write-enabled, 1 bit is sufficient; in this case, the nonvolatile memory cell 23 is EEPR.
It can be configured with one OM memory cell. To write to this nonvolatile memory cell, simply inputting the address and data as usual will only write to the cell matrix 10, so the addresses CADD, R
Perform special operations or preprocessing on ADD and data from I10 buffer 17. The operation procedure is set in the software I/ware protection logic 26, and the protection logic 26 receives the CADD, RADD, and data and determines that writing to the nonvolatile memory cell 23 occurs when the data is predetermined. Then, when a normal write address and write data are sent, the data is written to the corresponding address in the cell matrix 10, and at the same time, data 1 "write prohibited", for example, is written to the nonvolatile memory cell.

To write this write-protection command, do the following: B.S.
In the cell section, there are memory cells of 64 word lines, for example, in which company codes, device codes, etc. are written. In the present invention, the remaining memory cells of this ES cell section are used to store the software. ! (Writing is prohibited) and the protection release (Writable) information is written in advance.

This information is also written in the same way as the company code, for example, if the software is to be protected, the information code is written to the ES Nanatsugawa, and if the same protection is to be canceled, the information code is written to the ESS cell section.

The column address for 64 Hyde is A.

~6 bits of A5 are enough, and non-volatile memory cell 23
When "1" is written in A5, the read column decoder 18 fixes A5 to O in response to this. Therefore, only the first 32 bytes (data of BS cell 1) of the 64 bytes of read data can pass through the read column gate, and thus the information code representing the software protection is read out.

If the information written in the non-volatile memory cell 23 is software protection release ``0'''', the read column decoder 18 fixes A5 to 1 in response to this, and as a result, among the successive data of 64 hides, Second half 32 high l-(
The data in the ES cell 2 becomes readable, and the software protection release information code therein is read out.

Also, when performing this reading, a voltage that is not normally used (such as 12V versus 5V) is applied to the special operation terminal A9.

At this time, the high voltage detection buffer 29 disables the aforementioned row address buffer 14 etc. and enables ESD.

If a write prohibition pattern is written in the nonvolatile memory cell 23, writing to the cell matrix 10 is prohibited through the path of the software share protection logic 26 and the control logic 25. Note that even if writing is prohibited, if you perform a special operation (inputting a specific address, etc.) to write, Il [next or all (64) Writing can be performed.

[Effects of the Invention] As explained above, according to the present invention, nonvolatile memory cells (
It is convenient because the data stored in the memory function control storage unit can be virtually read out, and there is no need to actually perform writing or other relevant processing to know whether it is prohibited or permitted, as in the past.

[Brief explanation of drawings]

Figure 1 is a diagram of the principle of the present invention. FIG. 2 is a schematic diagram showing an embodiment of the present invention.

Claims (1)

[Claims] 1. A semiconductor comprising a cell group (11, 12) in which predetermined information is written in a cell matrix along its specific word line, and also comprising a nonvolatile memory cell (23) for controlling memory functions. In the memory element, memory function control information to be written to the nonvolatile memory cell is
The predetermined information is written in a part of the cell group to be written, and read data from the cell group is selected according to the storage information of the nonvolatile memory cell, and the storage information of the nonvolatile memory cell is read to the outside. A semiconductor memory element characterized by being made possible.