JP2005078489A - Microcontroller and its control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcontroller for preventing performance deterioration by retention of a flash memory to improve the reliability, and its control method. <P>SOLUTION: At the time of power activation or power reset cancellation, a write state of a memory cell array 11a in the flash memory 11 is detected. By rewriting into a memory cell in the write state, the reliability of the microcontroller in use afterward is improved. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a microcontroller device in which a flash memory is embedded and has a rewriting function in the memory cell, and a control method thereof.

  Currently, flash memory is widely used for memory cards and the like. In addition to being used alone, it is mounted together with a CPU on a single chip and used as a part of a circuit of a microcontroller device.

  As the application spreads in this way, the features of flash memory have been utilized and solutions to problems have been attempted.

  A flash memory has a problem called retention in which a threshold voltage in a written state is lowered after data is written to a memory cell. This is a phenomenon in which the threshold voltage decreases with time as charges injected into the tunnel insulating film constituting the gate escape from the tunnel insulating film. That is, this is a problem peculiar to a flash memory in which charges are injected into a tunnel insulating film constituting a gate to form a data write state.

  Conventionally, a circuit for verifying this phenomenon as a flash memory has been provided for such retention, and a function for rewriting data in a memory cell whose threshold voltage has decreased is provided to maintain the performance. As a result, for example, a device in which a microcontroller device having a flash memory is mounted has been prevented from being degraded by retention (see, for example, Patent Document 1).

  However, in the future, as the control by the microcontroller device having the flash memory to various devices spreads, the microcontroller device is required to improve the reliability corresponding to the device to which the device is applied. Yes.

The flash memory not only satisfies basic performance, but also requires detailed specification settings that match the environment in which it is used or the situation in which it is used. Therefore, with regard to retention in the flash memory, taking into account the application of the microcontroller device to the device, there is a problem of dealing with setting the rewrite timing and the like.
Japanese Patent Laid-Open No. 2001-14869 (page 4, FIG. 1)

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a microcontroller with higher reliability in a microcontroller device in which a flash memory is embedded, in which performance of the memory cell is prevented from being reduced by retention. An apparatus and a control method thereof are provided.

  In order to solve the above-mentioned problems, a first invention of the present invention comprises, as a microcontroller device, a CPU, a flash memory, and a control unit for controlling the operation of the flash memory. It is characterized by having verification means for verifying the write state of the memory cell in the flash memory at the time of release, and rewrite means for rewriting the memory cell in the write state.

  The second invention of the present invention is a control method of a microcontroller device comprising a CPU, a flash memory, and a control unit for controlling the operation of the flash memory, and at the time of power-on or power-release reset, The writing state of the memory cell of the flash memory is verified, and rewriting is performed on the memory cell in the writing state.

  According to the present invention, when the power is turned on or when the power reset is released, the writing state of the memory cell in the flash memory is verified, and the flash memory is mixedly mounted by rewriting the memory cell in the writing state. Reliability is improved when using the existing microcontroller device.

  Embodiments of the present invention will be described below with reference to the drawings.

  A circuit block diagram of an embodiment of a microcontroller device according to the present invention is shown in FIG. The flash memory 11 is, for example, a NOR flash memory. The CPU 10a controls the entire microcontroller device 10 and generates and outputs a program for controlling an external device based on the data written in the flash memory 11. The control unit 12 controls the operation of the flash memory 11 in response to a control instruction from the CPU 10a. Input / output of these data is performed through the bus line 10b. The relationship among the circuits including the verification circuit 13, the voltage generation circuit 14, the voltage selection circuit 15, and the comparison data storage circuit 16 will be described below.

  FIG. 2 is a circuit block diagram showing in detail the flash memory 11 and the control unit 12 of the microcontroller device shown in FIG. 2 also shows a verification circuit 13, a voltage generation circuit 14, a voltage selection circuit 15, and a comparison data storage circuit 16.

  In the flash memory 11, the address buffer circuit 11b holds an address input by the CPU through a bus line (both not shown). The row decoder 11c and the column decoder 11d read the address from the address buffer circuit 11b and access the selected memory cell in the memory cell array 11a. On the other hand, the data input through the bus line is held by the data input buffer circuit 11f and stored in the memory cell at the selected address through the sense amplifier 11e. The data output buffer circuit 11g holds data read from the memory cell array 11a and transmits it to the CPU or verification circuit.

  The control unit 12 holds the command input from the CPU in the command buffer circuit 12a. The command decoder 12b reads the command of the command buffer circuit 12a, and the sequence control circuit 12c generates a control signal for controlling a series of operation sequences. The sequence control circuit 12c includes a program counter 12d that measures the number of rewrites.

  The voltage generation circuit 14 is a circuit that generates a voltage for determining whether or not each memory cell in the memory cell array 11a is in a write state and a voltage for detecting a threshold voltage drop of the memory cell due to retention. The voltage selection circuit 15 selects either the voltage for determining the write state in the voltage generation circuit 14 or the voltage for detecting the threshold voltage drop, and selects the memory cell array 11a as the gate voltage via the row decoder 11c. This is a circuit that supplies the memory cell array.

  The verification circuit 13 verifies that data is normally written at the time of data writing or rewriting, and transmits the result to the control unit 12. That is, the verification circuit 13 reads the written data from the memory cell array 11a via the data output buffer circuit 11g, and collates the coincidence with the write data transmitted from the data input buffer circuit 11f. If they do not match, further writing is performed.

  The verification circuit 13 determines whether each memory cell in the memory cell array 11a is in a write state when the power is turned on or when the power reset is released. That is, the verification circuit 13 reads the written data from the memory cell array 11a via the data output buffer circuit 11g, compares it with the data transmitted from the control unit 12 to the comparison data storage unit 16, and sends the result to the control unit 12. provide feedback.

  FIG. 3 is a flowchart showing a series of operation sequences from the time when the microcontroller device according to this embodiment is turned on or the time when the power supply is reset until the data is rewritten. This will be described with reference to FIGS.

  At the time of turning on the power of the device in which the microcontroller device 10 is mounted or when releasing the power reset after trouble or the like, the power is also turned on in the microcontroller device 10 or the power reset is released and the operation is started. (Step S1).

  Along with the start of the operation, a rewrite mode command, which is one of the programs built in the CPU 10a, is input to the command buffer circuit 12a of the control unit 12 (step S2). When this command is input, the command decoder 12b reads the data in the command buffer circuit 12a, and the sequence control circuit 12c generates a series of operation sequences related to rewriting.

  The sequence control circuit 12c reads the number of times of repair related to the writing of the memory cell measured by the program counter 12d (step S3). (Step S10). The CPU 10a outputs a signal giving a warning to the device on which the microcontroller device 10 is mounted. Further, since no further operation is required, the sequence ends (step S11).

  By this processing, it is possible to prevent the performance degradation due to the retention of the flash memory 11 and to maintain the reliability of the microcontroller device 10.

  On the other hand, when the number of times of repair is less than the specified value, the actual rewrite mode is executed. First, the address of the memory cell of the flash memory 11 is designated (step S4). The row decoder 11c and the column decoder 11d read the address stored in the address buffer circuit 11b, and select a memory cell from the memory cell array 11a.

  Subsequently, verification of data writing is performed for the designated memory cell (step S5). As a series of sequences, first, the voltage selection circuit 15 selects a voltage for determining the writing state generated in the voltage generation circuit 14, and supplies it as a gate voltage to the selected memory cell of the memory cell array 11a via the row decoder 11c. To do. Next, the data written in the designated memory cell is read via the data output buffer circuit 11 g and transmitted to the verification circuit 13. Further, the verification circuit 13 compares the data output from the control unit 12 to the comparison data storage circuit 16 and the data written in the memory cell described above. If they match, the verification circuit 13 is selected for data writing. It is determined as a memory cell.

  On the other hand, if the data do not match, the verification circuit 13 determines that the memory cell is not selected for data writing. Since no further processing is performed for the non-selected memory cell, the series of sequences returns to the addressing of the memory cell to designate the next memory cell (step S4).

  If it is determined in step S5 that the memory cell is selected for data writing, the threshold voltage drop due to retention is next verified (step S6).

  The voltage selection circuit 15 selects a voltage generated by the voltage generation circuit 14 to detect a threshold voltage drop, and supplies the selected voltage to the selected memory cell of the memory cell array 11a through the row decoder 11c as a gate voltage. This voltage is set lower than the aforementioned threshold voltage determination voltage, and a memory cell in which data to be written is erased is detected.

  Next, the data written in the memory cell is read via the data output buffer circuit 11 f and transmitted to the verification circuit 13. Further, the verification circuit 13 compares the data output from the control unit 12 to the comparison data storage circuit 16 and the data written in the memory cell described above, and determines that the data can be read if they match. In this case, the series of sequences returns to addressing of the memory cell in order to specify the next memory cell (step S4).

  On the other hand, if the data do not match, the verification circuit 13 determines that the data written in the memory cell has been erased. In this case, next, data is rewritten to restore the data (step S7).

  Further, the verification circuit 13 notifies the program counter 12d of rewriting. The program counter 12d counts the number of times of repair (step S8), and when the number of times of repair reaches a specified value, sends an operation stop signal and a warning signal to the microcontroller device 10 to the CPU 10a (step S10). The CPU 10a outputs a signal giving a warning to the device on which the microcontroller device 10 is mounted. Further, since no further operation is required, the sequence ends (step S11).

  By this processing, it is possible to prevent the performance degradation due to the retention of the flash memory, and to improve the reliability of the microcontroller device 10.

  On the other hand, if the number of repairs is less than the specified value, the sequence returns to addressing the memory cell to specify the next memory cell (step S4).

  The above series of steps is sequentially executed for all the memory cells in the memory cell array 11a, and then ends (step S9).

  As described above in detail, according to this embodiment, in the microcontroller device including the flash memory, it is possible to prevent the performance degradation due to the retention of the flash memory, and to maintain the reliability of the microcontroller device.

  In addition, since data is rewritten only for memory cells whose threshold voltage has been lowered, power consumption associated with rewriting can be suppressed to a low level.

(Modification)
FIG. 4 shows the concept of retention in flash memory. FIG. 4 is a graph showing the frequency distribution of the threshold voltage of the memory cell after writing to the flash memory. For example, the distribution indicated by A is shown immediately after writing. Even when a flash memory is used, there is a memory cell in which the threshold voltage decreases with the passage of time. For example, the distribution shown in B is taken. Further, when time elapses, for example, the distribution shown in C is taken. Such a phenomenon that the threshold voltage of the memory cell is lowered is retention.

  Next, based on the above-described retention, a modified example related to the embodiment will be described.

  In the example, data was rewritten to the memory cell whose threshold voltage was lowered. However, when the distribution shown in FIG. 4C is taken, all the data is rewritten without distinguishing the memory cells whose threshold voltage has decreased. The memory cell to which data is written is overwritten. There is an advantage that the time required for rewriting is shortened. Further, as can be seen from FIG. 4, the determination of the erased state of the written data may be fluctuated by the gate voltage applied to the memory cell. Therefore, rewriting all data may increase reliability.

  Further, as shown in FIG. 4, the variation in threshold voltage has a continuous spread, and the setting of the voltage for detecting the threshold voltage drop shown in the embodiment is not limited to one, but a plurality. There may be.

  In addition, this invention is not limited to the Example mentioned above at all, It can implement in various changes within the range which does not deviate from the main point of this invention.

  The flash memory can be applied not only to a NOR flash memory, but also to a NAND flash memory, a flash memory having both NOR and NAND advantages, an AND flash memory, and the like.

  Although the case where a flash memory and a CPU are mixedly mounted as a microcontroller is shown, the present invention can also be applied to a case where a memory such as a DRAM is mounted.

The circuit block diagram which shows the Example of the microcontroller apparatus by this invention. The circuit block diagram in the Example of the microcontroller apparatus by this invention. The flowchart which shows the operation | movement sequence of data rewriting in the Example of the microcontroller apparatus by this invention. 4 is a graph showing the concept of memory cell retention in an embodiment of a microcontroller device according to the present invention;

Explanation of symbols

10 Microcontroller device 10a CPU
10b bus line 11 flash memory 12 control unit 13 verification circuit 14 voltage generation circuit 15 voltage selection circuit 16 comparison data storage circuit 11a memory cell array 11b address buffer circuit 11c row decoder 11d column decoder 11e sense amplifier 11f data input buffer circuit 11g data output buffer Circuit 12a Command buffer circuit 12b Command decoder 12c Sequence control circuit 12d Program counter

Claims (8)

CPU,
Flash memory,
A control unit for controlling the operation of the flash memory,
Verification means for verifying the write state of the memory cell in the flash memory at the time of power-on or power reset release,
A microcontroller device comprising: rewrite means for rewriting the memory cell in a write state. In the memory cell in the write state, a memory cell having a threshold voltage in the write state lower than a reference is detected, and the rewrite is performed only for the memory cell having a threshold voltage lower than the reference. The microcontroller device according to claim 1. 3. A measuring means for measuring the frequency of rewriting, a means for stopping operation when the frequency exceeds a specified number, and a means for issuing a warning to the outside. A microcontroller device according to claim 1. 4. The microcontroller according to claim 1, wherein a program for executing an operation of the flash memory when the power is turned on or when a power reset is released is built in the CPU. 5. apparatus. A control method of a microcontroller device comprising a CPU, a flash memory, and a control unit for controlling the operation of the flash memory,
A method for controlling a microcontroller device, comprising: verifying a write state of a memory cell of a flash memory and rewriting the memory cell in a write state when power is turned on or when a power reset is released. 2. The memory cell in the write state, wherein a memory cell having a threshold voltage lower than a reference is detected, and the rewrite is performed only for the memory cell having a threshold voltage lower than a reference. 6. A method for controlling a microcontroller device according to 5. The frequency of the rewriting is measured, and when the frequency exceeds a specified number, the operation is stopped and a warning is issued to the outside. Control method. The CPU has a built-in program for executing the operation of the flash memory when the power is turned on or when the power reset is released, and the CPU inputs the program to the control unit when the power is turned on or when the power reset is released. 8. The method of controlling a microcontroller device including a flash memory according to claim 5, wherein the unit decodes the program and controls the flash memory.

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