JPH07175725A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To provide a compact and inexpensive semiconductor memory device of large capacity which can protect the writing and reading operations of data using a password by means of a simple, compact and inexpensive circuit means, can keep the secrecy of stored data, and can prevent destruction of the stored data. CONSTITUTION:A semiconductor memory device consists of a semiconductor memory 2, a connector part 1 and a memory control part 3. The memory 2 includes a set password address comparing part 5 which has a set password storage area and outputs a coincidence signal to the part 3 when an address signal points the set password storage area, and a password collating part 4 which outputs a coincidence signal to the part 3 when the coincidence is secured between the input and set passwords. Then the part 3 reads out the set password and outputs it to the part 4 after reception of the coincidence signal from the part 5 and also continuously inhibits the accesses to the memory 2 until the coincidence signal is received from the part 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device used as an auxiliary memory device such as a computer, and more particularly to means for inhibiting writing and reading of a semiconductor memory by using a password.

[0002]

2. Description of the Related Art An IC card equipped with a semiconductor memory element is used as an auxiliary memory device such as a computer. This IC card includes a memory card which is a semiconductor memory device in which a CPU is mounted and only a memory element is mounted.

A memory card has the advantage of being compact and having a large storage capacity, but since anyone can read the data in the memory card, there is a problem in terms of protection of secrets, and anyone can write it. Therefore, there is a fear that once written data is accidentally erased or overwritten.

On the other hand, the IC card has a microprocessor and a semiconductor memory built in the card body, and a password is stored in advance and only when the data matches the data inputted from the outside, the writing or reading of the data with the IC card is performed. Is possible.

Therefore, in order to solve the above problems in the memory card, it is possible to mount a microprocessor on the memory card to perform password verification. However, in this case, since the microprocessor only performs password verification, it cannot be said that the microprocessor is being used effectively, and the cost performance is very low. Further, in general, a memory card is required to be as compact as possible and have a large storage capacity. Therefore, if the microprocessor is mounted on the memory card, the mounting space of the semiconductor memory is naturally reduced, which is disadvantageous for downsizing and increasing the capacity. Moreover, if a microprocessor is mounted, a semiconductor memory for storing a program for operating the microprocessor is also required, which is further disadvantageous.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks of the prior art. A first object of the present invention is a so-called memory card having no microcomputer, and an IC card having a microcomputer therein. It is intended to have a data protection function as well as.

A second object of the present invention is to provide a semiconductor memory device capable of writing and reading to and from a semiconductor memory by using a password only by adding a simple circuit.

[0008]

In order to achieve the above object, the present invention provides a semiconductor memory for storing various data, a connector portion for coupling with a reader / writer device, and input through the connector portion. A semiconductor memory device comprising a memory control unit for controlling writing into the semiconductor memory according to an instruction from the reader / writer device, wherein the memory control unit instructs the reader / writer device to write data to the semiconductor memory. Read / write permission mode and a prohibition mode that prohibits the reader / writer device from reading / writing data from / into the semiconductor memory, a flag is stored in the semiconductor memory, and the memory control unit is externally connected. It is always in the prohibit mode when power is supplied, and the reader / writer device passes the flag through the connector section. Instruction read of is input,
The gist is to shift to the permission mode when the flag has a predetermined value.

In order to achieve the above object, the present invention provides a semiconductor memory for storing various data, a connector portion for coupling with a reader / writer device, and an instruction from the reader / writer device input through the connector portion. According to a semiconductor memory device comprising a memory control unit for controlling reading of data from the semiconductor memory and writing of data to the semiconductor memory, the semiconductor memory has a setting password storage area in which a setting password is written. A setting password address comparing unit that outputs a specific signal to the memory control unit when the address signal input from the connector unit points to the setting password storage area; and a setting password output from the memory control unit. When the input password entered from the connector section matches, the memo A password collating unit that outputs a specific signal to the control unit, and the memory control unit reads out the set password from the set password storage area of the semiconductor memory when receiving the specific signal from the set password address comparison circuit. The purpose is to prohibit access to the semiconductor memory until a specific signal from the password verification circuit is received.

[0010]

According to this structure, when the semiconductor memory device is connected to the reader / writer device and the power is turned on, the memory control section is in the prohibition mode in which access to the semiconductor memory is prohibited. An instruction to read the flag stored in the semiconductor memory is input from the device, and if the flag has a predetermined value, the mode shifts to the permission mode, and otherwise, the prohibition mode continues.

When the semiconductor memory device is connected to the reader / writer device and the power is turned on, the memory control unit prohibits access to the semiconductor memory, and the reader / writer device addresses and input passwords in the set password storage area. When is input, the memory control unit reads the set password from the semiconductor memory based on the match signal from the set password address comparison unit and outputs it to the password collation unit.
When the password verification unit determines that the password matches the input password, the memory control unit releases the access prohibition to the semiconductor memory based on the match signal from the password verification unit.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of a memory card 100 according to the present invention. For the sake of clarity, some of the circuits are shown as blocks and the power supply, ground, etc. are omitted. In FIG. 1, 1 is a connector section, 2 is a semiconductor memory, 3 is a memory control section, 4 is a password collating section, and 5 is a set password address comparing section.

The connector section 1 connects the memory card 100 and the reader / writer device 200, and has a terminal 1a for receiving an address signal from the outside, a terminal 1e for exchanging a data signal, and a writing control. A terminal 1b for receiving a signal, a terminal 1c for receiving a read control signal,
It is composed of a terminal 1d and the like which receives control signals other than those for writing and reading. When the present invention is applied to a non-contact type memory card, the above-mentioned terminal is composed of a coil or a light sending / receiving means.

The semiconductor memory 2 may be either volatile or non-volatile, and 2a is a terminal for receiving an address signal, 2e is a terminal for exchanging a data signal, and 2c is a terminal for receiving a read control signal. In the description, a Low signal is used for reading) 2b is a terminal that receives a write control signal (in this description, a Low signal is used for writing). This semiconductor memory 2 has a set password storage area 2 in which the set password is written as shown in FIG.
01, a data storage area 202 for storing data, and a setting password is written in the setting password storage area 201 in advance.

The memory control section 3 receives an external control signal for writing and reading and controls an input / output of a data signal, and gates 14-2.
It is composed of 1.

The set password address comparison unit 5 compares the address input from the outside with the address of the set password storage area 201 in the semiconductor memory 2 and outputs a Low signal when they match and when they do not match. And a set password address comparison circuit 11 for outputting a High signal.

An embodiment of the set password address comparison circuit 11 is shown in FIG. Password address comparison circuit 1
The address signal 1a which is an input of 1 is a bus, and its constituent elements are 1a (A0), 1a (A1) to 1a (Ax). 1a (A0), 1a (A1) to 1a (Ax) are
It is input to the OR gates 301 to 30x. Also, in this figure, the set password address is "00 (H)".
An address is used, and one input of the OR gate 301 to the gate 30x is GND (ground). It goes without saying that when the set password address is other than the address "00 (H)", the input of these gates may be changed according to the set password address. The output of the gate 311 is
It becomes the output of the password address comparison circuit 11.

The password verification unit 4 is an input password which is input from the outside through a data signal and the semiconductor memory 2.
The password comparison circuit 13 compares the set passwords output from the device, outputs a Low signal thereafter when they match, and outputs a High signal when they do not match.

An embodiment of the password verification circuit 13 is shown in FIG.
It shows in (a). 1e (D0) to 1e (D7) are data signals 1e from the connector section 1 of the password verification circuit 13.
And each of the data signals that make up 2e (D0) to 2e
e (D7) is each data signal forming the data signal 2e from the semiconductor memory 2. Get these signals
The data is collated by inputting the gates 401 to 408 and using the outputs of these gates as the inputs of the gate 411.

The circuit composed of the gates 412 to 415, the capacitor 417, and the resistor 416 is a circuit for maintaining the signal of the gate 411, which is the result of password verification, at the time of power-off, that is, until the memory card is removed. One end of the resistor 416 is connected to a power supply terminal to which power is supplied from the reader / writer device of the connector unit 1 (not shown), and one end of the capacitor 417 is connected to the ground.

The capacitor 417 and the resistor 416 are temporarily set to the gate 413 at the time of mounting the memory card reader / writer.
It outputs the ow signal and then outputs the High signal. With this configuration, when the memory card is connected to the reader / writer device and power is supplied,
The password verification circuit 13 outputs a High signal, and when the passwords match thereafter, it continues to output a Low signal, and when they do not match, it continues to output a High signal.

In this circuit, the width of the data is 8 bits, but when it is 16 bits, 32 bits, etc., the gate 40 is used.
It goes without saying that it can be easily realized by increasing the number of gates 1 to 408. When the set password is made up of a plurality of words, it may be realized by combining the circuits shown in FIG.

The specific operation of the circuit will be described with reference to FIG. After the power is turned on, a High signal is output from the password verification circuit 13 and the set password address comparison circuit 11, and this is input to the gate 16, gate 17, and gate 18. The outputs of the gate 16, the gate 17, and the gate 18 output a High signal regardless of the other input. The gate 19 receives the High signal from the gate 16 and the gate 17, and outputs the High signal. As a result, the output of the High signal from the gate 19 and the gate 18 is transmitted to the read control signal 2c and the write control signal 2b of the semiconductor memory 2, and the semiconductor memory 2 is in a write / read disabled state. In this circuit, writing and reading to the outside are prohibited in all areas of the semiconductor memory 2 for the sake of simplification of description, but the circuit is partially changed such as connecting the semiconductor memory 2 in blocks. It goes without saying that it is possible to prohibit only a part of the area of the semiconductor memory 2 or to prohibit only one of writing and reading to the outside.

Next, a password verification method for canceling the prohibition state will be described. First, an operation of writing an input password from the outside to the setting password storage area 201 in the semiconductor memory 2 via the logic writer device 200 is performed. That is, in the connector section 1, the address signal terminal 1a is the address of the setting password storage area 201 in the semiconductor memory 2, the data signal terminal 1e is the input password, and the write control signal terminal 1b is Low. Input the signal. However, at this point, as described above, the write control signal terminal 2b of the semiconductor memory 2 is set to H level.
Since the high signal is input, the contents of the semiconductor memory 2 will not be rewritten. The address input to the address signal terminal 1a is the set password address comparison circuit 1
1 and the input address and the address of the set password storage area 201 match, the set password address comparison circuit 11 outputs a Low signal. This Lo
The signal of the w signal is transmitted to the input of the gate 16. The other input of the gate 16 is Lo from the write control signal 1b.
Since the w signal and the High signal from the password verification circuit 13 are input, the output of the gate 16 becomes the Low signal. This Low signal is transmitted to the gate 19, whereby the output of the gate 19 becomes the Low signal. The output of this Low signal is the read control signal terminal 2 of the semiconductor memory 2.
Then, the semiconductor memory 2 is in a read state,
The setting password is output from the terminal 2e of the semiconductor memory 2. That is, the writing control signal from the outside is converted into the reading control signal in the memory control unit 3 and is transmitted to the semiconductor memory 2.

A point to be noted here is that there is no collision of data on the data signal. Since the output of the password verification circuit 13 is a high signal, this high signal is transmitted to the inputs of the gate 14 and the gate 15, and
Both outputs of one gate become High signals,
The gh signal is the gate 20 of the data input / output control unit 30.
And 21 high-impedance control terminals. As a result, the data signal lines 1e and 2e are electrically disconnected by the gate 20 and the gate 21, and as a result, the setting password output from the semiconductor memory 2 and the input from the connector section 1 are input. The applied input password does not collide with the data signal. The setting password and the input password are collated by the password collation circuit 13, and if the collation result is coincident, the password collation circuit 13 thereafter outputs Low.
Continue to output signals. The output of this Low signal is gate 14, gate 15, gate 16, gate 17, gate 1
8 is input to cancel the write-protected and external read prohibited states of the semiconductor memory 2.

The operation of canceling the read / write inhibition state by the password verification can be expressed as shown in the flow chart of FIG.

The memory card 100 is powered on (S
51), a part or all of the area of the semiconductor memory 2 is in a prohibited state for writing and / or reading to the outside (S52). In order to cancel this prohibition state, the input password is written in the set password storage area of the semiconductor memory 2 (S53). By performing this operation, the memory control unit 3 and the password collation unit 4 collate the input password and the set password (S54), and if they match, the prohibition state is released (S55). If they do not match, the read / write protected state continues. Once released, this state continues until the power is turned off. In this case, when the power is turned on again after the power is turned off, the state returns to the initial state, and the semiconductor memory 2 is in a read / write prohibited state.

In the above embodiment, if the passwords match, the read / write protected state continues until the power is turned off. However, this password verification operation is performed for each read / write. It is also possible to do so. In this case, the password verification circuit is shown in FIG.
The output terminal e (out) of (a) is connected to the terminal e (i of the circuit composed of the 4-bit shift register shown in FIG. 3B.
n) is connected. This further improves the security of the data.

It is to be noted that, when the prohibited state is released as described above, all the storage areas of the semiconductor memory 2 can be written and read when the setting password is changed, so that the setting password of the semiconductor memory 2 can be changed. -Do by specifying the address of the storage area and rewriting the contents.

Next, a second embodiment will be described with reference to FIG.
6, the same parts as those in FIG. 1 are indicated by the same symbols. In the first embodiment, after the power is turned on, the password write and external read prohibition states cannot be released unless the password verification operation is performed. This embodiment is improved in this embodiment.

As shown in FIG. 7, the semiconductor memory 2 has an area other than the set password storage area 201 and the data storage area 202, and part or all of the area of the semiconductor memory 2 depending on the verification result of the password verification circuit 13. Both writing and reading to the outside, or a password collation mode for canceling the prohibition state of either one, or both writing to the entire area of the semiconductor memory 2 and reading to the outside regardless of the collation result are started. It has a selection information storage area 203 for selecting two modes, that is, the standard mode to be canceled from the above.

In terms of circuitry, it comprises a selection information address comparison circuit 22 which compares an address input from the outside with an address in the selection information storage area 203 in the semiconductor memory and outputs a Low signal when they match. The memory control unit 3 has a selection information address comparison unit 3, and the contents of the selection information read from the semiconductor memory 2 are written to the semiconductor memory 2 and written to the outside regardless of the comparison result of the password comparison circuit 13. If it is to cancel both readings from the beginning, the selection information collating circuit 2 that outputs a Low signal thereafter
5, a gate 23, and a gate 24.

The selection information address comparison unit 3 can be realized with a circuit configuration almost the same as the set password address comparison circuit 11, and the description thereof will be omitted. Further, when the selection information collating circuit 25 also sets "00 (H)" to the standard mode, it can be realized with a circuit configuration almost the same as that of the set address / address comparing circuit 11 only by setting the input of the gate to the data signal terminal 2e. is there.

When the power is turned on, the password verification circuit 13 and the set password address comparison circuit 11 output Hi.
The gh signal is output, and this is the gate 16 and the gate 1
7 is input to the gate 18. Gate 16, Gate 1
7. The output of gate 18 is High regardless of the other input.
The h signal is output. The gate 19 receives the High signal from the gate 16 and the gate 17, and outputs the High signal. As a result, Hi from the gate 19 and the gate 18
The output of the gh signal is transmitted to the read control signal terminal 2a and the write control signal terminal 2b of the semiconductor memory 2,
The semiconductor memory 2 is in a prohibited state for both writing and reading.

Next, the reader / writer device 200 performs an operation of designating an address of the selection information storage area in the semiconductor memory 2 and reading the content thereof. Even in this prohibition state, the selection information storage area 203 in the semiconductor memory 2 can be read because the selection information address comparison circuit 22 outputs a Low signal.

Specifically, in the connector section 1, the address signal input terminal 1a receives the address of the selection information storage area 203, the read control signal input terminal 1c receives the Low signal, and the data signal input / output terminal. The contents of the selection information storage area 203 are read from 1e.

The address of the selection information storage area 203 input to the address signal input terminal 1a is transmitted to the selection information address comparison circuit 22 and outputs a Low signal if they match. The gate 23, which has received the output of the Low signal, has an output Lo regardless of the input from the password verification circuit 13.
It becomes the w signal. The output of the gate 17 which receives the low signal output and the low signal from the read control signal is L
It becomes an ow signal and is transmitted as a Low signal through the gate 19 to the read control signal terminal 2c of the semiconductor memory 2. Further, the gate 1 which receives the output of the low signal from the gate 23 and the output of the low signal from the input / output control circuit 12
The output of 5 becomes a Low signal and is input to the high impedance control terminal of the gate 21. As a result, the data signal is output. In this way, the contents of the selection information storage area in the second semiconductor memory are output to the reader / writer device 200 through the connector unit 1.

At the same time, the contents of this selection information storage area are transmitted to the selection information collating circuit 25, and if the contents of this selection information storage area indicate the standard mode,
The selection information matching circuit 25 outputs a Low signal. This L
The output of the ow signal is transmitted to the gate 24 and the gate 24
Output to the Low signal, and the gates 14 and
The inputs of the gate 16, the gate 17, the gate 18, the gate 23, and the gate 15 are set to the Low signal. As a result, the input levels of the write control signal terminal 1b and the read control signal terminal 1c input from the connector unit 1 are directly transmitted to the write control signal terminal 2b and the read control signal terminal 2c of the semiconductor memory 2. Become, semiconductor memory 2
The write prohibition and external read prohibition status are released.

If the content of the selected information storage area indicates the password verification mode, the output of the selected information verification circuit 25 becomes a high signal, and the password verification circuit releases the prohibited state. It depends on the collation result of 13.

The above operation can be represented as in the flow chart of FIG. In the memory card 100, after the power is turned on (S81), a part or all of the area of the semiconductor memory 2 is in a write-protected state and / or read-out to the outside is in a prohibited state (S82).

Next, the contents of the selection information storage area in the semiconductor memory 2 are read (S83). If the contents indicate the standard mode, the password verification operation is skipped and the read / write prohibited state is immediately entered. Is canceled (S8
7). If there is an instruction for the password verification mode, the same operation as in FIG. 5 is performed (S85 to S87).

A standard of a memory card, which is a kind of semiconductor memory device issued by the Japan Electronic Industry Development Association (for example, IC
Memory card guideline Ver. In 4.1), after the power is turned on, the start address of the attribute memory of the memory card in which the attribute information and the like of the memory card are first stored is' 0.
The address (H) 'is to be read. At this address "0 (H)", data "01 (H)" which is a tuple ID of device information or an invalid tuple ID.
Is data "00 (H)" or tuple chain end tuple ID "FF (H)". If the data at address '0 (H)'
If the data is data "00 (H)" which is an invalid tuple ID, the data at the address "01 (H)" which is the next address.
The data will be read out, and this data must also be the above-mentioned three types.

Therefore, in a system using a memory card, the address '0 (H)' is always read first. Therefore, the selection information storage area 203 is shown in FIG.
As shown in FIG.
If it is arranged at the address (H) ', the reader / writer device 20
Address' 0 without changing the software of 0
The address (H) 'can be read out first and the contents of the selected information storage area can be transmitted to the selected information collating circuit 25. Invalid tuple ID at address '0 (H)'
Even if the data "00 (H)" is written and the selection information is written at the address "01 (H)", the same effect can be obtained.

The contents of the selection information storage area are
When the data is '01 (H) ', the writing and / or the reading to / from the outside of a part or all of the area of this semiconductor memory is canceled from the beginning regardless of the matching result of the password matching circuit 13. In this sense, the system that has read this selected information storage area recognizes this memory card as a standard memory card and, at the same time, can release the prohibited state by this operation.

Therefore, there is an advantage that one reader / writer device can be used for both the memory card of the present invention and the memory card of the standard specifications without changing the software.

In this case, naturally, the data of the selection information is the data.
When the data is other than "01 (H)", the password verification circuit 13
It means that the prohibition state of writing and reading of the semiconductor memory is released according to the result of the collation. Similarly,
The data "00 (H)" or the data "FF (H)" is released from the beginning of the writing and reading of the entire area of the semiconductor memory 2 regardless of the verification result of the password verification circuit 13. When the data other than the data '00 (H) 'or the data other than the data'FF (H)', the password verification circuit 1
The same effect can be obtained even if the prohibition state of writing and reading of the semiconductor memory is released according to the collation result of 3.

FIG. 9 shows a third embodiment of the present invention. In the first embodiment, a counter 26 for counting the number of password verification operations and a gate 27 are added to the password verification unit 4. However, if the collation work is performed a certain number of times or more, after that, the prohibited state cannot be released even if the collation results match. 9, the same parts as those in FIG. 1 are indicated by the same symbols. The output of the counter 26 is
When the number of times is less than a certain number of times, a Low signal is output, and when the number of times is more than a certain number of times, a High signal is output.

As a result, a person who does not know the password can
By trying to input the password many times, it is possible to know the correct password and prevent the illegal reading or writing of the data of the memory card.

The counter circuit 26 and the gate 27 in this embodiment can be added to the above-mentioned second embodiment.

FIG. 10 shows a fourth embodiment of the present invention, in which a semiconductor memory 2 uses a volatile memory which requires backup with a battery. By removing this battery, the volatile memory is removed. 5 is a circuit diagram of a memory card in which the contents of data are erased, but at the same time, the write-in or read-out prohibited state of the semiconductor memory 2 can be released. 10, the same parts as those in FIG. 1 are indicated by the same symbols.

Here, the power supply terminal 1f of the connector section 1 is connected to the power supply terminal 2f of the semiconductor memory 2 via a diode 33. A battery 31 is also connected to this terminal 2f via a diode. The battery 31 is further connected via a gate 29 to a gate 28 that receives the output of the password verification circuit 13, and the output of the gate 28 is supplied to the gates 14 to 18.

When the battery 31 is removed, the output of the gate 29 changes from the High signal to the Low signal. The output of the gate 28 receiving this output becomes a Low signal, and the prohibited state is released. If the password is forgotten, the contents of the volatile semiconductor memory will be erased by removing the battery, but this will release the write and read inhibit status, and the memory card itself can be reused. it can. Since the contents of the volatile semiconductor memory disappear,
The contents of this volatile semiconductor memory will not be known to others.

The diode 32 is a battery 31 and a connector section 1.
The power supply terminal 1f of the semiconductor memory 2 serves to switch the power supply from the power supply terminal 1f of the power supply terminal 1f, thereby supplying either voltage to the power supply 2f of the semiconductor memory 2. Further, the diode 33 prevents the current of the battery 31 from flowing back to the power source 1f of the connector section 1. The resistor 30 is connected to the gate 2 when the battery 31 is removed.
The input of 9 is made a Low signal.

It should be noted that the present embodiment is further enhanced in function by adding a configuration for switching the mode by the selection information as in the second embodiment and a configuration for providing a counter circuit for recording error recovery as in the third embodiment. It is also possible to implement various memory cards.

In the above embodiment, the setting password is input using the write control signal input terminal 1b. However, if there is a margin in the signal line, the setting password can be set separately from the write control signal input terminal 1b. The same effect can be obtained by providing a terminal 1g (not shown) for a negative input signal in the connector portion 1 and thereby inputting a setting password.

FIG. 11 shows a fifth embodiment of the present invention, in which a non-volatile memory capable of reading and writing data is used as the memory 2. In the figure, the first
The same parts as those in the embodiment are indicated by the same symbols.

The present embodiment is different from the first embodiment in that a flash memory is used as the semiconductor memory 2 and that the reset command comparison circuit 32 is provided with a reset circuit 33.

The reset command comparison circuit 32 determines whether or not the command input from the reader / writer device 200 is a reset command, and outputs a match signal when the commands match, and a terminal 1e for exchanging data signals.
Is connected to the reset circuit 33.

The reset circuit 33 erases the contents of the data storage area 202 and the set password storage area 201 of the semiconductor memory 2 in response to the coincidence signal of the reset command comparison circuit 32, and the CPU and the memory storing the reset flow. It consists of and. The reset circuit is connected to the address signal terminal 2a, the data signal terminal 2e, the write control signal line 2b, the read control signal line 2c, and the password verification unit 4.

Next, the operation of this embodiment will be described with reference to FIGS. 11 and 12.

First, when the reader / writer device 200 gives an instruction to write a reset command into the semiconductor memory 2, the reset command comparison circuit 32 causes the data I / O to operate.
It is determined whether the data from the terminal 1e is a reset command. When the reset command comparison circuit 32 determines that the input data is the reset command, the coincidence signal is sent to the reset circuit 33. When the reset circuit 33 receives the coincidence signal from the reset command comparison circuit 32, the CPU therein operates according to the flow shown in FIG. The reset circuit 33 normally outputs a HIGH signal to the password verification unit 4.

First, the reset circuit 33 sends a chip erase command to the flash memory 2 (S10).
1). As a result, password and data erasing processing is started inside the flash memory 2. And
It is determined whether the erasing process is completed by monitoring the status signal from the memory (S102). If it is determined that the error has not been completed, it is determined whether or not an error has occurred during the erase process of the flash memory (S105). If it is determined that no error has occurred, the process returns to S102 to continue monitoring.

When it is determined in S102 that the erasing process has been completed, a LOW signal is output to the password collating section 4 (S103), and the process is terminated. This forcibly cancels the write-read prohibition state.

On the other hand, if it is determined in S105 that an error has occurred, the HIGH signal is continuously output to the password collating section 4, and the read / write prohibited state continues.

As described above, in the present embodiment, the entire flash memory 2 is erased to forcibly cancel the read / write prohibited state. Therefore, if the cardholder forgets the password. Also, it is possible to restore the use of the card in exchange for erasing the stored data.

Although the embodiment in which the present invention is applied to a memory card has been described above, the present invention is not limited to this, and it goes without saying that the present invention can be applied to so-called general semiconductor devices such as memory packs and semiconductor disks. .

[0067]

As described above, according to the present invention, in a so-called memory card which does not have a microcomputer with simple, small-sized, and inexpensive circuit means, the I card having a microcomputer is provided.
Like the C card, it can have a data protection function. Further, it is possible to realize the protection of writing and reading of the data by using the password, and by this, it is possible to maintain the confidentiality of the storage data and prevent the destruction of the storage data. A semiconductor memory device can be provided at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a memory card according to the present invention.

FIG. 2 is a circuit diagram showing an embodiment of a set password address comparison circuit.

FIG. 3 is a circuit diagram showing an embodiment of a password matching circuit.

FIG. 4 is a memory configuration diagram of a semiconductor memory of a memory card.

FIG. 5 is a flowchart showing a processing procedure of a memory card.

FIG. 6 is a block diagram showing a second embodiment of the memory card.

FIG. 7 is a memory configuration diagram of a semiconductor memory of a memory card.

FIG. 8 is a flowchart showing a processing procedure of a memory card.

FIG. 9 is a block diagram showing a third embodiment of the memory card.

FIG. 10 is a block diagram showing a fourth embodiment of a semiconductor memory device.

FIG. 11 is a block diagram showing a fifth embodiment of the semiconductor memory device.

FIG. 12 is a flowchart showing the processing procedure of the fifth embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Connector part 2 Semiconductor memory 3 Memory control part 4 Password collation part 11 Setting password comparison circuit 12 Input / output control circuit 100 Memory card 200 Memory card reader / writer device 22 Selection information address comparison circuit 25 Selection information comparison circuit 26 counter circuit 30 battery 31 resistance

Claims (11)

[Claims] 1. A semiconductor memory for storing various data,
A connector unit for coupling with the reader / writer device, and controlling reading of data from the semiconductor memory and writing of data into the semiconductor memory according to an instruction from the reader / writer device input via the connector unit. A semiconductor memory device comprising a memory control unit, wherein the semiconductor memory device outputs a coincidence signal to the memory control unit when an address signal input from the connector unit points to a set password storage area. And a password collating unit that outputs a coincidence signal to the memory control unit when the setting password output from the memory control unit and the input password input from the connector unit match, the semiconductor memory has a setting password. Has a setting password storage area in which The memory control unit reads the set password from the set password storage area of the semiconductor memory when the coincidence signal is received from the set password address comparison unit, outputs the set password to the password collation unit, and the semiconductor memory until the coincidence signal from the password collation unit is received. A semiconductor memory device characterized in that access to a memory is prohibited. 2. The semiconductor memory according to claim 1, wherein the semiconductor memory can write data when receiving a write control signal from the connector portion, and can read data when receiving a read control signal. When the memory control unit receives a coincidence signal from the set password address comparison circuit, the write control signal from the connector unit is read out and converted into a control signal to read the set password from the set password storage area of the semiconductor memory. A semiconductor memory device characterized by outputting to a collating unit. 3. The selection information address comparison according to claim 1, wherein the semiconductor memory device outputs a match signal to a memory control unit when an address signal input from the connector unit points to a selection information storage area. The semiconductor memory has a selection information storage area in which selection information for instructing either a standard mode or a password verification mode is written, and the memory control unit has a match from the selection information address comparison unit. A semiconductor memory device, wherein when the signal is received, the selection information is referred to, and in the standard mode, the access inhibition to the semiconductor memory is released. 4. The selection information storage area according to claim 3, having the address "0 (H) 'of the semiconductor memory or an address next to invalid data starting from the address" 0 (H)'. A semiconductor memory device characterized by the above. 5. The content of the selection information storage area of the semiconductor memory according to claim 4, which is represented by 1 byte, and the standard mode is data 00 (H) ', data 01 (H)' or Either data FF (H) 'and password verification mode is data 00 (H)', data 01
(H) 'and data FF (H)' other than the semiconductor memory device. 6. The set password written in the semiconductor memory 2 according to claim 1, after the write-in or read-out prohibited state of the semiconductor memory 2 is released according to the collation result of the password collation unit. A semiconductor memory device characterized in that it can be freely changed and read. 7. The password verifying unit according to claim 1, wherein a counter means for counting the number of times of verification is added to the password verification unit, and when the verification operation is performed a predetermined number of times or more, a setting password and an input password are thereafter added. The semiconductor memory device is characterized in that it does not output a specific signal to the memory control unit even if the two match. 8. The volatile memory according to claim 1, wherein a part or all of the semiconductor memory is backed up by a battery, and the battery is removed to remove the volatile memory data.
The semiconductor memory device is characterized in that the contents of the memory are erased, but at the same time, the write-in or read-out prohibited state of the semiconductor memory 2 can be released. 9. The semiconductor memory according to claim 1, wherein the semiconductor memory is a flash memory, the semiconductor memory device further includes a reset command comparison circuit and a reset circuit, and the reset command comparison circuit is input from a reader / writer. A semiconductor memory device characterized in that when a command matches a predetermined reset command, a match signal is output, and the reset circuit resets the contents stored in the semiconductor memory by outputting the match signal. 10. A semiconductor memory for storing various data, and a connector portion for coupling with a reader / writer device,
Inputting via the connector unit has a permission mode for permitting the reader / writer device to read / write data from / into the semiconductor memory and a prohibition mode to inhibit the reader / writer device from reading / writing data in to / from the semiconductor memory. A semiconductor memory device configured to control writing into the semiconductor memory according to an instruction from the reader / writer device that has been written, a flag is stored in the semiconductor memory, and the memory control unit is an external device. When the power is supplied from the device, it is always in the prohibit mode, and when the reading / writing instruction of the flag is input from the reader / writer device through the connector section and the flag has a predetermined value, the mode is changed to the permit mode. A semiconductor memory device characterized by: 11. A semiconductor memory for storing various data, and a connector portion for coupling with a reader / writer device,
A semiconductor memory device comprising: a memory control unit that controls reading of data from the semiconductor memory and writing of data into the semiconductor memory according to an instruction from the reader / writer device input via the connector unit; The semiconductor memory device includes a selection information address comparison unit that outputs a coincidence signal to the memory control unit when the address signal input from the connector unit points to the selection information storage area, and the semiconductor memory has the selection information. The memory control unit has a written selection information storage area, and when the memory control unit receives a match signal from the selection information address comparison unit, the selection information is read from the selection information storage region of the semiconductor memory, and the selection information has a predetermined value. Read data in the semiconductor memory and write data in the semiconductor memory only when The semiconductor memory device which is characterized in that to enable