JP3668514B2 - Semiconductor memory device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor memory device used as an auxiliary memory device such as a computer, and more particularly to a means for prohibiting writing and reading of a semiconductor memory using a password.
[0002]
[Prior art]
IC cards equipped with semiconductor memory elements are used as auxiliary storage devices such as computers. This IC card includes a memory card that is a semiconductor memory device on which a CPU is mounted and a memory element only.
[0003]
The memory card has a merit that it is compact and has a large storage capacity, but since anyone can read the data in the memory card, there is a problem in terms of secret protection, and anyone can write it. The written data may be erased or overwritten by mistake.
[0004]
On the other hand, the IC card has a microprocessor and a semiconductor memory built in the card body, and it is possible to write or read data on the IC card only when the password is stored in advance and matches the data inputted from the outside. To do.
[0005]
Therefore, in order to solve the problems in the memory card, it is possible to mount a microprocessor in the memory card and perform password verification. However, in this case, since the microprocessor only performs password verification, it cannot be said that the microprocessor is effectively used, and the cost performance is very low. In general, a memory card is required to be as compact as possible and have a large storage capacity. For this reason, if the microprocessor is mounted on the memory card, the space for mounting the semiconductor memory is naturally reduced, which is disadvantageous for compactness and large capacity. In addition, when a microprocessor is mounted, a semiconductor memory for storing a program for operating the microprocessor is required, which is further disadvantageous.
[0006]
[Problems to be solved by the invention]
The present invention has been made in view of the above-mentioned drawbacks of the prior art. The first object of the present invention is a so-called memory card that does not have a microcomputer, and has a data protection function similar to an IC card that has an internal microcomputer. The purpose is to make it.
[0007]
A second object of the present invention is to provide a semiconductor memory device that can write and read a semiconductor memory by using a password only by adding a simple circuit.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, the present invention stores various data. And a setting password storage area in which the setting password is written A semiconductor memory, a connector unit for coupling to the reader / writer device, and the semiconductor memory in accordance with an instruction from the reader / writer device input via the connector unit In a semiconductor memory device comprising a memory control unit that controls reading of data and writing of data into the semiconductor memory, the semiconductor memory device has an address signal input from the connector unit indicating a set password storage area. A setting password address comparison unit that outputs a coincidence signal to the memory control unit and a setting password output from the memory control unit and an input password input from the connector unit to the memory control unit. A password verification unit that outputs a match signal, and when the memory control unit receives a match signal from the set password address comparison unit, it reads the set password from the set password storage area of the semiconductor memory and outputs it to the password verification unit The semiconductor until receiving a match signal from the password verification unit As well as prohibiting access to memory, and outputs to the password comparison section converts the write control signal to the out control signal read reads the set password from the set password storage area of the semiconductor memory from the connector portion This is the gist.
[0010]
[Action]
According to such a configuration, when power is turned on while the semiconductor memory device is connected to the reader / writer device, the memory control unit is in a prohibited mode in which access to the semiconductor memory is prohibited. When an instruction to read a flag stored in the memory is input and the flag is a predetermined value, the mode is shifted to a permission mode, and otherwise, the prohibit mode is continued.
[0011]
In addition, when the power is turned on while the semiconductor memory device is connected to the reader / writer device, the memory control unit prohibits access to the semiconductor memory, and the address and input password of the set password storage area are input from the reader / writer device. Then, based on the match signal from the set password address comparison unit, the memory control unit reads the set password from the semiconductor memory, outputs it to the password verification unit, and when the password verification unit determines a match with the input password, the password verification unit The memory control unit cancels the prohibition of access to the semiconductor memory based on the coincidence signal from.
[0012]
【Example】
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of a memory card 100 according to the present invention. For ease of viewing, some of the circuits are shown as blocks, and the power supply, ground, and the like are omitted. In FIG. 1, 1 is a connector unit, 2 is a semiconductor memory, 3 is a memory control unit, 4 is a password verification unit, and 5 is a set password address comparison unit.
[0013]
The connector unit 1 couples the memory card 100 and the reader / writer device 200, and receives a terminal 1a for receiving an address signal from the outside, a terminal 1e for exchanging data signals, and a writing control signal. A terminal 1b, a terminal 1c for receiving a read control signal, a terminal 1d for receiving a control signal other than for writing and reading, and the like. When the present invention is applied to a non-contact type memory card, the terminal is composed of a coil or light transmitting / receiving means.
[0014]
The semiconductor memory 2 may be either volatile or nonvolatile. 2a is a terminal for receiving an address signal, 2e is a terminal for exchanging data signals, and 2c is a terminal for receiving a read control signal (in this description, Low). 2b is a terminal that receives a write control signal (in this description, it is assumed that data is written with a Low signal). As shown in FIG. 4, the semiconductor memory 2 includes a setting password storage area 201 for writing a setting password and a data storage area 202 for storing data. The setting password storage area 201 has a setting password in advance. Is written.
[0015]
The memory control unit 3 includes an input / output control circuit 12 for controlling input / output of data signals in response to external control signals for writing and reading, and gates 14 to 21.
[0016]
The set password address comparison unit 5 compares an address input from the outside with the address of the set password storage area 201 in the semiconductor memory 2 and outputs a Low signal when they match, and a High signal when they do not match Is set from the set password address comparison circuit 11.
[0017]
An embodiment of the set password address comparison circuit 11 is shown in FIG. An address signal 1a which is an input of the password address comparison circuit 11 is a bus, and its components are 1a (A0) and 1a (A1) to 1a (Ax). 1a (A0) and 1a (A1) to 1a (Ax) are input to the OR gate 301 to the gate 30x. In this figure, the set password address is '00 (H) ', and one of the inputs of the OR gate 301 to the gate 30x is GND (ground). Needless to say, when the set password address is other than the address '00 (H) ', the input of these gates may be changed according to the set password address. The output of the gate 311 becomes the output of the password address comparison circuit 11.
[0018]
The password collating unit 4 compares the input password inputted from the outside through the data signal and the set password outputted from the semiconductor memory 2, and outputs a Low signal thereafter if they match. If they do not match, the password verification circuit 13 outputs a High signal.
[0019]
One embodiment of the password verification circuit 13 is shown in FIG. 1e (D0) to 1e (D7) are data signals constituting the data signal 1e from the connector 1 of the password verification circuit 13, and 2e (D0) to 2e (D7). Are data signals constituting the data signal 2 e from the semiconductor memory 2. These signals are input to the gates 401 to 408, and the outputs of these gates are input to the gate 411, whereby the data is collated.
[0020]
A circuit composed of the gates 412 to 415, the capacitor 417, and the resistor 416 is a circuit for maintaining the signal of the gate 411 that is the password verification result when the power is shut down, that is, until the memory card is removed. One end of the resistor 416 is connected to a power supply terminal that receives power from a reader / writer device of the connector unit 1 (not shown), and one end of the capacitor 417 is connected to the ground.
[0021]
The capacitor 417 and the resistor 416 function to temporarily output a Low signal to the gate 413 and then output a High signal when the memory card reader / writer is mounted. With this configuration, when the memory card is connected to the reader / writer device and power is supplied, the password verification circuit 13 outputs a High signal, and then continues to output a Low signal when the passwords match. If they do not match, the High signal is continuously output.
[0022]
In this circuit, the data width is 8 bits, but it goes without saying that it can be easily realized by increasing the number of gates 401 to 408 in the case of 16 bits, 32 bits, or the like. If the set password is a plurality of words, it can be realized by combining the circuits of FIG.
[0023]
A specific circuit operation will be described with reference to FIG. After the power is turned on, a high signal is output from the password verification circuit 13 and the set password address comparison circuit 11, and this is input to the gate 16, the gate 17, and the gate 18. The outputs of the gate 16, the gate 17, and the gate 18 output a high signal regardless of the other input. The gate 19 receives the High signal from the gate 16 and the gate 17 and outputs the High signal. As a result, the output of the High signal from the gate 19 and the gate 18 is transmitted to the read control signal 2c and the write control signal 2b of the semiconductor memory 2, and the semiconductor memory 2 is prohibited from being written and read. In this circuit, in order to simplify the explanation, writing and reading to the outside are prohibited in all areas of the semiconductor memory 2, but the circuit is partially changed such that the semiconductor memory 2 is divided into blocks and connected. It goes without saying that it is possible to prohibit only a partial area of the semiconductor memory 2 or only one of writing and reading to the outside.
[0024]
Next, a password verification method for canceling this prohibited state will be described. First, an operation of writing the input password to the set password storage area 201 in the semiconductor memory 2 is performed from the outside via the logical writer device 200. In other words, in the connector section 1, the address of the set password storage area 201 in the semiconductor memory 2 is assigned to the address signal terminal 1a, the input password is supplied to the data signal terminal 1e, and the write control signal terminal 1b is set to Low. Input the signal. However, at this time, since the High signal is input to the write control signal terminal 2b of the semiconductor memory 2 as described above, the contents of the semiconductor memory 2 are not rewritten. The address input to the address signal terminal 1a is transmitted to the set password address comparison circuit 11, and when the input address matches the address of the set password storage area 201, the set password address comparison circuit 11 outputs a low signal. Is output. This Low signal is transmitted to the input of the gate 16. The other inputs of the gate 16 are the Low signal from the write control signal 1b and the High signal from the password collating circuit 13, so the output of the gate 16 is the Low signal. This Low signal is transmitted to the gate 19, whereby the output of the gate 19 becomes a Low signal. The output of this Low signal is transmitted to the read control signal terminal 2c of the semiconductor memory 2, the semiconductor memory 2 enters the read state, and the set password is output from the terminal 2e of the semiconductor memory 2. That is, an external write control signal is converted into a read control signal in the memory control unit 3 and transmitted to the semiconductor memory 2.
[0025]
It should be noted that there is no data collision on the data signal. Since the output of the password verification circuit 13 is a High signal, this High signal is transmitted to the inputs of the gate 14 and the gate 15, and the outputs of the two gates are both High signals. The signal is input to the high impedance control terminals of the gates 20 and 21 of the data input / output control unit 30. As a result, the data signal lines 1e and 2e are electrically disconnected at the gate 20 and the gate 21. As a result, the set password output from the semiconductor memory 2 and the connector 1 are input. Input passwords do not collide on the data signal. When the set password and the input password are collated by the password collating circuit 13 and the collation result is the same, the Low signal is continuously output from the password collating circuit 13 thereafter. The output of this Low signal is input to the gate 14, the gate 15, the gate 16, the gate 17, and the gate 18, thereby preventing the semiconductor memory 2 from being written and read out to the outside. Canceled.
[0026]
The operation of canceling the read / write prohibited state by password verification can be expressed as shown in the flowchart of FIG.
[0027]
After the power is turned on (S51), the memory card 100 is in a state where a part or all of the semiconductor memory 2 is prohibited from writing and / or reading to the outside (S52). In order to cancel this prohibition state, an operation of writing the input password into the set password storage area of the semiconductor memory 2 is performed (S53). By performing this work, the memory control unit 3 and the password collation unit 4 collate the input password and the set password (S54), and if they match, the prohibition state is canceled (S55). If they do not match, reading and writing are prohibited. Once released, this state continues until the power is turned off. In this case, when the power is turned on again after the power is turned off, the state returns to the initial state, and the read / write state of the semiconductor memory 2 is disabled.
[0028]
By the way, in the above embodiment, if the passwords match, the read / write prohibited state continues until the power is turned off. However, this password verification operation may be performed for each read / write. Is possible. In this case, the password verification circuit has a configuration in which the output terminal e (out) of FIG. 3A is connected to the terminal e (in) of the circuit formed of the 4-bit shift register shown in FIG. 3B. This further improves data security.
[0029]
Note that the change of the set password can be written and read in all the storage areas of the semiconductor memory 2 when the prohibited state is released as described above. This is done by specifying the address of the area and rewriting its contents.
[0030]
Next, a second embodiment will be described with reference to FIG. In FIG. 6, the same components as those in FIG. 1 are denoted by the same symbols. In the first embodiment, after the power is turned on, the state of prohibiting writing to the semiconductor memory 2 and reading to the outside is not released unless the password verification operation is always performed. This is an improvement of this embodiment.
[0031]
As shown in FIG. 7, in the semiconductor memory 2, in addition to the set password storage area 201 and the data storage area 202, a part or all of the area of the semiconductor memory 2 can be written according to the verification result of the password verification circuit 13. Either the password verification mode for canceling the prohibition state of either or both of reading to the outside, or both writing to the entire area of the semiconductor memory 2 and reading to the outside are canceled from the beginning regardless of the verification result. It has a selection information storage area 203 for selecting either the standard mode or the two modes.
[0032]
Further, in terms of circuit, a selection information address comprising a selection information address comparison circuit 22 which compares an address input from the outside with an address of the selection information storage area 203 in the semiconductor memory and outputs a Low signal when they match. A comparison unit 3 is provided, and the memory control unit 3 reads the contents of the selection information read from the semiconductor memory 2 regardless of the collation result of the password collation circuit 13 and writes the data to the semiconductor memory 2 and reads it to the outside. If both are to be canceled from the beginning, it has a selection information collating circuit 25 for outputting a Low signal thereafter, a gate 23, and a gate 24.
[0033]
Note that the selection information address comparison unit 3 can be realized with substantially the same circuit configuration as the set password address comparison circuit 11, and a description thereof will be omitted. Further, the selection information matching circuit 25 can also be realized with substantially the same circuit configuration as the setting address address comparison circuit 11 only by setting the gate input to the data signal terminal 2e when '00 (H) 'is set to the standard mode. is there.
[0034]
When the power is turned on, a high signal is output from the password verification circuit 13 and the set password address comparison circuit 11, and this is input to the gate 16, the gate 17, and the gate 18. . The outputs of the gate 16, the gate 17, and the gate 18 output a high signal regardless of the other input. The gate 19 receives the High signal from the gate 16 and the gate 17 and outputs the High signal. As a result, the output of the High signal from the gate 19 and the gate 18 is transmitted to the read control signal terminal 2a and the write control signal terminal 2b of the semiconductor memory 2, and the semiconductor memory 2 is in a prohibited state for both writing and reading. Become.
[0035]
Next, the reader / writer device 200 performs an operation of designating an address of the selected information storage area in the semiconductor memory 2 and reading the contents. Even in this prohibited state, the selection information storage area 203 in the semiconductor memory 2 can be read because the selection information address comparison circuit 22 outputs a Low signal.
[0036]
Specifically, in the connector unit 1, the address of the selection information storage area 203 is input to the address signal input terminal 1a, the Low signal is input to the read control signal input terminal 1c, and selected from the data signal input / output terminal 1e. The contents of the information storage area 203 are read out.
[0037]
The address of the selection information storage area 203 input to the address signal input terminal 1a is transmitted to the selection information address comparison circuit 22, and outputs a Low signal if they match. The gate 23 receiving the output of the Low signal outputs a Low signal regardless of the input from the password verification circuit 13. The output of the gate 17 that has received the output of the Low signal and the Low signal from the read control signal becomes the Low signal, and passes through the gate 19 to the read control signal terminal 2c of the semiconductor memory 2 as a Low signal. Communicated. Further, the output of the gate 23 and the output of the gate 15 receiving the output of the low signal from the input / output control circuit 12 become the low signal and are input to the high impedance control terminal of the gate 21. Is done. As a result, the data signal is output. In this way, the contents of the selection information storage area in the two semiconductor memories are output to the reader / writer device 200 through the connector unit 1.
[0038]
At the same time, the contents of the selection information storage area are transmitted to the selection information verification circuit 25. If the selection information storage area indicates the standard mode, the selection information verification circuit 25 outputs a Low signal. To do. The output of the Low signal is transmitted to the gate 24, and the output of the gate 24 is changed to the Low signal. Then, the gate 14, gate 16, gate 17, gate 18, gate 18, -The inputs of the gate 23 and the gate 15 are set to the low signal. As a result, the input levels of the write control signal terminal 1b and the read control signal terminal 1c input from the connector unit 1 are directly transmitted to the write control signal terminal 2b and the read control signal terminal 2c of the semiconductor memory 2. Thus, the state of prohibiting writing to the semiconductor memory 2 and reading to the outside is released.
[0039]
If the content of the selection information storage area indicates the password collation mode, the output of the selection information collation circuit 25 is a High signal, and the prohibition state is canceled by the collation of the password collation circuit 13. It depends on the result.
[0040]
The above operation can be expressed as shown in the flowchart of FIG. After the power is turned on (S81), the memory card 100 is in a state where a part or all of the semiconductor memory 2 is in a state where both writing and / or reading to the outside are prohibited (S82).
[0041]
Next, the content of the selection information storage area in the semiconductor memory 2 is read (S83). If this content indicates the standard mode, the password verification operation is skipped and the read / write prohibition state is immediately released. (S87). If there is an instruction for the password collation mode, the same operation as in FIG. 5 is performed (S85 to S87).
[0042]
The memory card standard (for example, IC memory card guideline Ver. 4.1), which is a kind of semiconductor memory device issued by the Japan Electronic Industry Development Association, describes the attribute information of the memory card first after the power is turned on. '0 (H)' which is the head address of the attribute memory in which is stored. At this address “0 (H)”, data “01 (H)” which is a tuple ID of device information, data “00 (H)” which is an invalid tuple ID, or a tuple chain It is specified that it is one of the data 'FF (H)' as the end tuple ID. If the data at address "0 (H)" is data "00 (H)" that is an invalid tuple ID, data at address "01 (H)" is the next address. This data must also be the above three types.
[0043]
For this reason, in a system using a memory card, the address '0 (H)' is always read first. Therefore, if the selection information storage area 203 is arranged at the address “0 (H)” which is the head address of the semiconductor memory 2 as shown in FIG. The address 0 (H) ′ can be read first, and the contents of the selection information storage area can be transmitted to the selection information matching circuit 25. The same effect can be obtained by writing data “00 (H)”, which is an invalid tuple ID, at address “0 (H)” and writing selection information at address “01 (H)”.
[0044]
When the content of the selection information storage area is data "01 (H)", writing or writing to a part or all of the area of the semiconductor memory is performed regardless of the collation result of the password collation circuit 13. In the sense that both or one of the readings is released from the beginning, the system that reads this selected information storage area recognizes this memory card as a standard memory card, and at the same time is prohibited by this operation. Can also be released.
[0045]
Therefore, there is a merit that it can be used for both the memory card of the present invention and the memory card of the standard specification without changing the software with one reader / writer device.
[0046]
In this case, naturally, when the data of the selection information is other than the data '01 (H) ', the prohibition state of writing and reading of the semiconductor memory is canceled according to the collation result of the password collation circuit 13. Makes sense. Similarly, data '00 (H) 'or data' FF (H) 'is written to or read from the entire area of the semiconductor memory 2 regardless of the verification result of the password verification circuit 13. In the case of data other than data '00 (H) 'or data other than' FF (H) ', the writing / reading of this semiconductor memory is performed according to the collation result of the password collation circuit 13. The same effect can be obtained even in the meaning of canceling the prohibited state.
[0047]
FIG. 9 shows a third embodiment of the present invention. In the first embodiment, a counter 26 and a gate 27 for counting the number of times of password verification work are added to the password verification unit 4 so as to maintain a constant value. If the collation work is performed more than the number of times, the prohibited state cannot be canceled after that even if the collation results match. 9, the same parts as those in FIG. 1 are denoted by the same symbols. The counter 26 is configured to output a Low signal when the output is less than a certain number of times, and to output a High signal when the output is more than a certain number of times.
[0048]
This prevents a person who does not know the password from trying to input the password many times, knowing the correct password, and illegally reading or writing data on the memory card. it can.
[0049]
Incidentally, the counter circuit 26 and the gate 27 in this embodiment can be added to the second embodiment described above.
[0050]
FIG. 10 shows a fourth embodiment of the present invention, in which a volatile memory that needs to be backed up by a battery is used for the semiconductor memory 2, and by removing this battery, the data of the volatile memory is removed. FIG. 3 is a circuit diagram of a memory card in which the contents of the data are erased, but at the same time, the state of prohibiting writing to the semiconductor memory 2 or reading to the outside can be canceled. 10, the same components as those in FIG. 1 are denoted by the same symbols.
[0051]
Here, the power supply terminal 1 f of the connector unit 1 is connected to the power supply terminal 2 f of the semiconductor memory 2 via the diode 33. The battery 31 is also connected to the terminal 2f via a diode. The battery 31 is further connected via a gate 29 to a gate 28 that receives the output of the password verification circuit 13 and the output of the gate 28 is supplied to the gates 14 to 18.
[0052]
When the battery 31 is removed, the output of the gate 29 changes from a high signal to a low signal. Upon receiving this output, the output of the gate 28 becomes a Low signal, and the prohibited state is released. If the password is forgotten, the contents of the volatile semiconductor memory will be erased by removing the battery. However, the write and read prohibition status is canceled, so the memory card itself can be used again. it can. Since the contents of the volatile semiconductor memory disappear, the contents of the volatile semiconductor memory are not known to others.
[0053]
The diode 32 functions to switch between the battery 31 and the power supplied from the power supply terminal 1 f of the connector unit 1, whereby either voltage is supplied to the power supply 2 f of the semiconductor memory 2. The diode 33 prevents the current of the battery 31 from flowing back to the power source 1 f of the connector unit 1. The resistor 30 makes the input of the gate 29 a Low signal when the battery 31 is removed.
[0054]
In addition, in this embodiment, by adding a configuration in which the mode is switched by selection information as in the second embodiment and a configuration in which a counter circuit for recording error recovery is provided as in the third embodiment, a more sophisticated memory card is provided. It is also possible to implement.
[0055]
In the above embodiment, the setting password is input using the writing control signal input terminal 1b. However, if there is a margin in the signal line, the setting password input is performed separately from the writing control signal input terminal 1b. The same effect can be obtained even if a signal terminal 1g (not shown) is provided in the connector section 1 and a setting password is input.
[0056]
FIG. 11 shows a fifth embodiment of the present invention, in which a nonvolatile memory capable of reading and writing data is used for the memory 2. In the figure, the same parts as those in the first embodiment are indicated by the same symbols.
[0057]
This embodiment differs from the first embodiment in that a flash memory is used for the semiconductor memory 2 and that a reset circuit 33 is provided in the reset command comparison circuit 32.
[0058]
The reset command comparison circuit 32 determines whether or not the command input from the reader / writer device 200 is a reset command, and outputs a coincidence signal if the command is coincident with the terminal 1e for exchanging data signals and the reset circuit. 33.
[0059]
The reset circuit 33 erases the contents of the data storage area 202 and the set password storage area 201 of the semiconductor memory 2 in response to the coincidence signal of the reset command comparison circuit 32, and is composed of a CPU and a memory storing a reset flow. Has been. The reset circuit is connected to the address signal terminal 2a, the data signal terminal 2e, the write control signal line 2b, the read control signal line 2c, and the password verification unit 4.
[0060]
Next, the operation of this embodiment will be described with reference to FIGS.
[0061]
First, when an operation to write a reset command to the semiconductor memory 2 is instructed from the reader / writer device 200, the reset command comparison circuit 32 determines whether or not the data from the data I / O terminal 1e is a reset command. When the reset command comparison circuit 32 determines that the input data is a reset command, it sends a match signal to the reset circuit 33. When the reset circuit 33 receives the coincidence signal from the reset command comparison circuit 32, the internal CPU operates according to the flow shown in FIG. The reset circuit 33 outputs a HIGH signal to the normal password verification unit 4.
[0062]
First, the reset circuit 33 sends a chip erase command to the flash memory 2 (S101). As a result, the password and data erasing process is started inside the flash memory 2. Then, it is determined whether or not the erasure process is completed by monitoring a status signal from the memory (S102). If it is determined that the error has not been completed, it is determined whether or not an error has occurred during the flash memory erasing process (S105). If it is determined that no error has occurred, the process returns to S102 and monitoring is continued.
[0063]
If it is determined in S102 that the erasure process has been completed, a LOW signal is output to the password verification unit 4 (S103), and the process ends. This forcibly releases the read / write prohibition state.
[0064]
On the other hand, if it is determined in S105 that an error has occurred, the HIGH signal is continuously output to the password verification unit 4 and the read / write prohibited state continues.
[0065]
As described above, in this embodiment, the entire flash memory 2 is erased to forcibly release the read / write prohibition state. Therefore, even if the cardholder forgets the password, the memory is stored. The use of cards can be reinstated for data erasure and exchange.
[0066]
As described above, the embodiments in which the present invention is applied to the memory card have been described. However, the present invention is not limited to this, and it is needless to say that the present invention can be applied to so-called semiconductor devices such as memory packs and semiconductor disks.
[0067]
【The invention's effect】
As described above, according to the present invention, a so-called memory card that does not have a microcomputer can be provided with a data protection function in the same manner as an IC card having a microcomputer inside, with simple, small, and inexpensive circuit means. In addition, data write and read protection using passwords can be realized, which makes it possible to maintain confidentiality of stored data and to prevent destruction of stored data. A semiconductor memory device can be provided at low cost.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a memory card according to the present invention.
FIG. 2 is a circuit diagram showing one embodiment of a set password address comparison circuit;
FIG. 3 is a circuit diagram showing one embodiment of a password verification circuit.
FIG. 4 is a memory configuration diagram of a semiconductor memory of a memory card.
FIG. 5 is a flowchart showing a processing procedure of the memory card.
FIG. 6 is a block diagram showing a second embodiment of the memory card.
FIG. 7 is a memory configuration diagram of a semiconductor memory of a memory card.
FIG. 8 is a flowchart showing a processing procedure of the memory card.
FIG. 9 is a block diagram showing a third embodiment of the memory card.
FIG. 10 is a block diagram showing a fourth embodiment of the semiconductor memory device.
FIG. 11 is a block diagram showing a fifth embodiment of the semiconductor memory device.
FIG. 12 is a flowchart showing a processing procedure of the fifth embodiment.
[Explanation of symbols]
1 Connector part
2 Semiconductor memory
3 Memory control unit
4 password verification unit
11 Setting password comparison circuit
12 I / O control circuit
100 memory card
200 Memory card reader / writer
22 Selection information address comparison circuit
25 Selection information verification circuit
26 Counter circuit
30 batteries
31 Resistance

Claims (8)

From a semiconductor memory having a setting password storage area in which various data are stored and a setting password is written, a connector unit for coupling to the reader / writer device, and a reader / writer device input via the connector unit In a semiconductor memory device comprising a memory control unit that controls reading of data in the semiconductor memory and writing of data into the semiconductor memory according to the instructions of
The semiconductor memory device has a setting password address comparison unit that outputs a coincidence signal to the memory control unit when the address signal input from the connector unit points to a setting password storage area;
Possess a password comparison section for outputting a coincidence signal to the case set output from the memory controller password input password input from the connector portion matches the memory controller,
When the memory control unit receives a match signal from the set password address comparison unit, the memory control unit reads the set password from the set password storage area of the semiconductor memory, outputs the set password to the password verification unit, and continues to receive the match signal from the password verification unit A semiconductor that prohibits access to a memory, reads out a write control signal from a connector section, converts it into a control signal, reads a set password from a set password storage area of the semiconductor memory, and outputs the set password to a password verification section Storage device. In claim 1,
The semiconductor memory device includes a selection information address comparison unit that outputs a coincidence signal to the memory control unit when the address signal input from the connector unit points to a selection information storage area,
The semiconductor memory has a selection information storage area in which selection information indicating either the standard mode or the password verification mode is written,
The memory control unit refers to the selection information when receiving a coincidence signal from the selection information address comparison unit, and cancels the prohibition of access to the semiconductor memory in the standard mode. .   3. The semiconductor memory according to claim 2, wherein the selection information storage area is provided at an address '0 (H)' address of the semiconductor memory or an address next to invalid data starting from the address '0 (H)' address. apparatus.   4. The content of the selection information storage area of the semiconductor memory according to claim 3, wherein the standard mode is any one of data “00 (H)”, data “01 (H)”, and data “FF (H)”. A semiconductor memory device characterized in that the password verification mode is any one other than data '00 (H) ', data '01 (H)', and data 'FF (H)'.   2. The setting password written in the semiconductor memory can be freely changed and read after the write or read prohibition state of the semiconductor memory 2 is canceled according to the verification result of the password verification unit. A semiconductor memory device.   The counter unit according to claim 1, wherein a counter means for counting the number of verifications is added to the password verification unit, and when the verification operation is performed a predetermined number of times or more, even if the set password and the input password subsequently match, the memory control unit A semiconductor memory device characterized by not outputting a specific signal.   2. The volatile memory according to claim 1, wherein a part or all of the semiconductor memory is a volatile memory backed up by a battery, and when the battery is removed, the data contents of the volatile memory disappear, but at the same time, the semiconductor memory 2 is written or read to the outside. A semiconductor memory device characterized in that the prohibited state can be canceled.   2. The semiconductor memory according to claim 1, wherein the semiconductor memory is a flash memory, and the semiconductor memory device further includes a reset command comparison circuit and a reset circuit, and the reset command comparison circuit receives a command input from a reader / writer as a predetermined reset command. A semiconductor memory device, wherein a match signal is output when the signal matches, and the reset circuit resets the stored contents of the semiconductor memory by the output of the match signal.

Images