JPH03147158A - Memory control circuit - Google Patents

Abstract

PURPOSE:To protect important data in a memory without fail by providing an OR circuit to receive various control signals and to output a signal to instruct the write inhibition of the memory. CONSTITUTION:An OR circuit 2 is provided to make a reset signal 3 and this signal 3 shows any one of an IO read signal (IORD), IO write signal (IOWT) and memory read signal (MRD) is executed at a destination where a program runs away. When the program erroneously runs away just after an instruction to instruct the write permission of the memory and the signal 3 is executed before a memory write signal (MWT) 6, a signal 5 is turned OFF by this signal 3. Afterwards, even when the MWT 6 is turned ON, it is refused by an AND circuit 7 and a write signal 8 to a memory 9 is not turned ON like d. Thus, the fear to destroy the data in the desired area of the memory is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control circuit, and particularly to a memory control circuit having a memory write permission circuit.

[Conventional technology]

An example of the configuration of a general device using a microprogram is shown in FIG. 3. In FIG. 3, a ROM 13 is a memory that stores a microprogram.
The memory control circuit 11 controls signals to the RAM 12 and writes and reads data to and from input/output devices (not shown).In particular, the RAM 12 stores data necessary for executing programs. There is an area for storing data.These data include data used as a substitute for dip switches and data representing system setting conditions, and there is a risk that this data may be unnecessarily rewritten or destroyed while the program is running. This is usually protected by the following methods:

First, all data written in the RAM 12 will be erased as soon as the device's power is cut off, so a battery is connected in parallel to the RAM 12's power supply as shown in Figure 3, so that even if the device's power is cut off, the RAM 12 There is a way to operate normally and retain data until the battery discharges and the voltage drops. Furthermore, there is a method of using a memory control circuit as shown in FIG. 4 to prevent erroneous writing to the above-mentioned data area to be protected during program execution. The data protection operation of this circuit will be explained below.

FIG. 5 is a timing diagram for explaining the operation of this memory control circuit. When the 10th instruction A that instructs memory write permission during program execution is executed, the signal 14 is turned on during the execution time a of the IO instruction A. , This signal 14 turns on the memory write permission signal 18 at the memory write permission port FI1117. Therefore, if a memory write command is executed while signal 18 is on, C
As shown in , the memory write signal (MWT) 16 is
A write signal 20 that is directly input to the memory 21 is generated by the D circuit 19 and output. Next, when executing the ■0 instruction B that instructs memory write prohibition to turn off the signal 18, the signal 15 is turned on during the execution time of the IO instruction 13 as shown in FIG. The permission circuit 17 turns off the memory write permission signal 18 . In this state, if a memory write command is executed, a memory write signal (MWT) 16 is generated as shown by d.
Even if it is turned on, it is rejected by the AND circuit 19 and the memory 21
In other words, when writing to an area of memory that you want to protect, always use these three
It is necessary to execute three instructions: one to enable memory writing, one to write to memory, and one to disable memory writing. Even if you point to the area you want to write, the write will not be performed because memory write permission has not been specified.
Your data will be protected.

[Problem to be solved by the invention]

As described above, conventional memory control circuits control whether writing to an area to be protected can be performed by executing three instructions: an instruction to enable memory writing, an instruction to write to memory, and an instruction to prohibit writing to memory. If the memory write permission signal remains on, such as when the program accidentally runs out of control after executing the ■0 instruction that instructs memory write permission, the area in the memory that you want to protect will There was also a drawback that data could be destroyed if data were written to.

An object of the present invention is to provide a memory control circuit that is less likely to destroy data in an area to be protected in memory even if a program accidentally goes out of control after an IO instruction that instructs memory write permission is executed. It is about providing.

[Means to solve the problem]

The memory control circuit of the present invention includes a memory write permission circuit that generates a memory write permission signal in response to a signal instructing permission or prohibition of memory writing, and a memory write permission circuit that directly controls the memory using the memory write permission signal and a memory write signal (MWT). The memory control circuit includes an AND circuit that generates a memory write signal to be controlled, and an OR circuit that receives various control signals and outputs a signal instructing memory write inhibition.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1 and 2 are a block diagram of a memory control circuit according to an embodiment of the present invention and a timing diagram explaining its operation, respectively. In the memory control circuit of FIG. 1, when an instruction (IO instruction) instructing memory write permission is issued, the period a during which this instruction is executed is as shown in FIGS. 2(A) and (B). Signal 1 is turned on and memory write permission port #! The memory write enable signal 5 outputted from 4 is turned on. While this memory write permission signal 5 is on, the memory write signal (MWT>6 is turned on to execute the memory write command, and the AND circuit 7 generates a write signal 8 for the memory 9. Also, the memory write permission is An OR circuit 2 is provided to generate a reset signal 3 for turning off the signal 5, and in this embodiment, the reset condition is an IO read signal ( IORD
>, IO write signal (IOWT), memory read signal (MRD) for memory, memory write signal (MWT)
) is on, signal 3 is turned on. In this embodiment, the memory write command is always executed immediately after the command for instructing memory write permission (command), and FIG. 2<A) shows the timing of this operation. In this case, a memory write signal (MWT) 6 is output while the signal 5 is on, and a write signal 8 is output as shown by C. Further, FIG. 2(B) shows a case where the program accidentally goes out of control immediately after an instruction to permit memory writing. In this case, when the program goes out of control, l0RD, l0WT, MR
When signal 3 indicating that one of D has been executed is executed before MWT 6, this signal 3 turns off signal 5, and even if MWT 6 is turned on afterwards, it is rejected by AND circuit 7 and the memory is The write signal 8 for 9 is not turned on as shown by d. Furthermore, when the program goes out of control, MWT is executed before l0RD, l0WT, and MRD, and it happens to point to the address that you want to protect, only for this address. Although it cannot be said that rewriting will not occur, even in such a case, the damage will be kept to a minimum because the MWT will then instruct the memory to be prohibited from writing.

In this embodiment, rORD, l0WT to reset the memory write enable signal 5.

The explanation has been given using four signals, MRD and MWT, but it is not limited to just these four signals, for example, two signals, MRD and MWT, or signals output in conjunction with completely different commands may be used. However, regarding MWT, This is effective because the memory write enable signal 5 is always turned off after the memory write command is executed.

〔Effect of the invention〕

As explained above, the present invention enables a memory write permission signal that is turned on by an IO command that instructs memory write permission to be turned off by executing any one of an IO read command, an IO write command, a memory read command, and a memory write command. By doing so, even if the program accidentally goes out of control after executing an instruction that instructs memory write protection, the memory contents can be prevented from being destroyed, and in the worst case, only one address will be destroyed. As a result, much of the contents of the memory will not be destroyed due to a program running out of control, as was the case in the past, and important data in the memory can be reliably protected.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a memory control circuit that is an embodiment of the present invention, Figures 2 (A) and (B) are schematic timing diagrams of the memory control circuit of Figure 1, and Figure 3 uses a microprogram. 4 is a block diagram of a conventional memory control circuit, and FIG. 5 is a schematic waveform diagram of the circuit shown in FIG. 4. 1...Signal indicating that memory write permission command is being executed;
2...OR circuit, 3...output signal from the OR circuit,
4...Memory write permission circuit, 5...Memory write permission signal, 6...Memory write signal (MWT),
7...AND circuit, 8...Write signal to memory,
9...Memory, 10...CPU, 11...Memory control circuit, 12...RAM, 13...ROM, 14
...Signal indicating that memory write permission command is being executed, 1
5... Signal representing memory write prohibition command, 16.
...Memory write signal<MWT), 17...Memory write permission circuit, 18...Memory write permission signal,
1...AND circuit, 20...Write signal to memory, 21...memory.

Claims (1)

[Claims] a memory write permission circuit that generates a memory write permission signal; an AND circuit that receives the memory write permission signal and the memory write signal and generates a memory write signal;
1. A memory control circuit comprising: an OR circuit that receives a plurality of control signals and outputs a signal instructing memory write inhibition.