JPH10254767A - Memory controller and memory system by the controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory controller which can construct respective bus architectures even if von Neumann and Harvard processors are connected on the same bus and which realizes access to other memories or a common memory. SOLUTION: A memory controller 3 recognizes the bus architectures by request signals 25 and 26 generated based on the securing of the bus from the von Neumann processor 4 and the Harvard processor 5 constructing the bus architectures. Then, von Neumann and Harvard types are constructed through the bus as the bus architectures and necessary information is obtained from the memories a1 and b2. The reading of an instruction and data at the same time can be realized if the memories a1 and b2 exist with such structure and the performance of the architectures is demonstrated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to access to a memory which is indispensable as a digital processing circuit including a processor such as an electronic computer. It is possible to mix a Harvard architecture and a standard (Neumann) architecture on the same bus. The present invention relates to a memory control device for constructing an access system performed via a bus.

[0002]

2. Description of the Related Art In a conventional access method in which a processor accesses a memory via a bus, a method called Harvard architecture in which instructions and data are obtained from different buses and a method called Neumann architecture in which instructions and data are transferred to one bus There is a method to acquire from. However, it has not been possible to construct a system in which both architectures are established by connecting devices such as processors for configuring these different bus architectures to the same bus and mixing both types on the bus.

In order to solve this problem, the following method has been conventionally considered. FIG. 3 is a diagram showing an example of a conventional system designed to make the above-mentioned Harvard and Neumann memories mutually accessible. In FIG. 3, the Harvard processor 33 accesses a program (memory a) and data (memory b) in the memories 41 and 42 in the architecture constructed by the Neumann processor 31 via the bus conversion block 32 to access the memory (memory a). The controller 30 needs to access the memory a41 or the memory b42 twice for instruction and data in total. Conversely, from the Neumann processor 31 to the memory c of the birdbird processor 33,
41 'and the memory d42' are accessed via the bus conversion block 32 by the respective memory controllers 34 and 35 for instructions and data.
It is necessary to access 1 'or the memory d42'.

FIG. 4 is a diagram showing an example of another conventional system for enabling the Harvard and Neumann-type mutual access. In FIG. 4, access from the Neuman processor 31 to the areas of the memory c41 'and the memory d42' of the Harvard processor 33 'requires a 32-bit input to a dedicated port of the Harvard processor 33'. Can only be done indirectly. In this example, the Harvard processor 33 'is provided with a dedicated port, and it is necessary to have the Neumann processor write to it or to have a memory read circuit in the dedicated port. In each of the above-described conventional examples, a similar system may be configured without each of the memory controllers 34 and 35 (broken line portions in FIGS. 3 and 4).

[0005]

As described above, when different bus architectures are mixed, data reading and writing from the memory are essentially different in the prior art, and the mixing of the Harvard architecture and the Neumann architecture on the same bus is not possible. I wasn't. The reason for this is that basically, when an attempt is made to access a certain address area, an instruction and data address are generated simultaneously in the Harvard architecture, but only one of an instruction and data is generated in the Neumann architecture. Is mentioned. As a result, a unique memory is connected for each processor constituting each architecture. The present invention has been made in view of the problems in the related art, and the Harvard architecture and the Neumann architecture can coexist on the same bus, that is, even if both the Neumann processor and the Harvard processor are connected to the bus, they are mutually connected. It is an object of the present invention to provide a memory control device capable of accessing the other or common memory.

[0006]

According to a first aspect of the present invention, a memory in a memory device having a processor provided for performing an operation of an access method according to a different bus architecture is accessed by the processor via a common bus. In a memory control device in a memory system configured to enable the above, a common control means for controlling reading and writing of the memory, and a bus input according to an access method according to the different bus architecture to the common control means. Signal processing means corresponding to each access method for processing as an input signal, and a control signal generated based on securing a bus in each processor and used for controlling the memory control device itself, according to the different bus architecture. A recognition means for recognizing a difference in access method; Selecting means for selecting the signal processing means corresponding to each access method according to the recognition result of the recognizing means, wherein a specific bus architecture selected from the different bus architectures is constructed by the operation of the selecting means. It is.

According to a second aspect of the present invention, in the first aspect of the invention, when the bus input by the processor has a configuration of a plurality of bits, and a plurality of memories are prepared as the memories, each of the plurality of memories is provided. On the other hand, a control bank as the common control means is provided for each of the plurality of memories so that reading and writing are performed simultaneously, and the signal processing means corresponding to each access method corresponding to the control bank is provided. .

According to a third aspect of the present invention, in the second aspect of the present invention, the processor is prepared to construct a Neumann bus architecture and a Harvard bus architecture, and the processor as the signal processing means corresponding to each access method. The bus master device allocates the control bank to a plurality of bits constituting the bus according to the bit order, thereby enabling construction of a Harvard bus architecture and a Neumann bus architecture.

According to a fourth aspect of the present invention, the memory is controlled by operating the memory control device according to any one of the first to third aspects by a bus input input via the common bus in accordance with the operation of the processor. A memory system that enables access to the memory by controlling and performing an operation of an access method using the different bus architecture.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the configuration of a memory device in which each processor is connected so as to constitute a Harvard architecture and a Neumann architecture, which processor is the memory controller according to the present invention accessing by an external input signal? And operates to recognize the information on the bus and to switch the bus architecture. This determines that the specified bit range is used for reading and writing data and programs based on the result of the circuit that determines which architecture,
It becomes possible to acquire necessary information and to reduce the number of connected memory points. At this time, it is also possible to improve the performance by incorporating a cache-like structure for each architecture in the memory control.
In this embodiment, in the case of access using the Harvard architecture, the access is started by the instruction memory circuit targeting the upper 16 bits, and at the same time, the data memory circuit targeting the lower 16 bits is also accessed. On the other hand, in the case of access using the Neumann architecture, an access is made to an address specified by 32 bits including upper and lower bits over a plurality of banks.

FIG. 1 is a conceptual diagram of a system having a memory controller according to the present invention and accessing a memory via a bus. In FIG. 1, in the memory controller 3, request signals 25 and 26 generated based on the reservation of a bus from each of the Neuman processor 4 and the Harvard processor 5 constructing each bus architecture.
And confirms the bus architecture, thereby constructing the Neumann type and the Harvard type via the bus 24 as the bus architecture, and operating to acquire necessary information from the memory element. With this structure, even when instructions and data are read out at the same time, it can be realized if there are two blocks of memory a1 and memory b2, and the performance of each architecture can be exhibited.

FIG. 2 is a more specific block diagram of the memory controller shown in FIG. This embodiment will be described in more detail with reference to FIG. In FIG.
In the memory controller 3 according to the present invention, as an example of the configuration, the processors 4 (see FIG. 1) and 1 that construct a Neumann-type architecture that processes 32-bit instructions are used.
A processor 5 (see FIG. 1) for constructing a Harvard architecture for processing 6-bit instructions is connected via a bus. Bus request 2 issued by arbitration of the bus by the method in the prior art
The bus architecture selection circuit 23, which detects which processor has secured the bus by 5, 26, and establishes a circuit for constructing the bus architecture, performs a selection operation according to the detection. When the Neumann processor 4 (see FIG. 1) secures the bus, the bus architecture selection circuit 23
The Neumann-type memory circuit 22 operates to recognize the 32-bit address output from the Neumann processor 4, and the Neumann-type memory circuit 22 reads the memory access circuits 15, 17 or the memory read / write circuits 16, 18 of the banks A13 and B14, respectively. 16-bit information is input to the memory A1 and the memory b2 specified by the 16-bit output from each of the bank A13 and the bank B14, so that input / output from / to the memory as the Neumann architecture can be performed.

Similarly, a Harvard processor 5 (FIG. 1,
When the bus is secured, the Harvard processing circuit 19 is operated by the bus architecture selection circuit 23, and the Harvard instruction memory circuit 20 stores the instruction in the upper 16 bits of 32 bits output from the Harvard processor 5. The memory a1 is accessed via either the memory access circuit 15 or the memory read / write circuit 16 of the bank A13, and the memory of the bank B14 in which instructions are stored in the lower 16 bits by the Harvard type data memory circuit 21. The memory b2 is accessed via either the access circuit 17 or the memory read / write circuit 18. As a result, data and instructions can be fetched simultaneously as a Harvard architecture. In this example, the bus is divided by upper and lower bit widths, but division by odd bits and even bits may be considered. Furthermore, two Harvard architecture processors each having an 8-bit width can generate two sets of 8-bit instructions and data to generate a total of four addresses.

[0014]

【The invention's effect】

Effect of Claim 1: According to the related art, different bus spaces must be provided and different memories must be arranged, so that the cost increases and data must be actually transferred between processors existing on different buses. Although a problem has occurred, the memory control device of the present invention can share a bus and a memory with different bus architectures, and is expected to reduce costs by reducing the number of components. Effect of Claim 2: In addition to the effect of Claim 1, it is possible to provide a memory control device that enables an operation of simultaneously reading and writing from each of a plurality of memories, and can configure a higher-performance memory device.

Effect of Claim 3: In addition to the effects of Claims 1 and 2, it is possible to provide a memory control device for constructing practical architectures of a Neumann-type and a Harvard-type bus architecture. According to the fourth aspect of the present invention, there is provided a memory system capable of sharing a bus and a memory in different bus architectures, and the system is simplified and cost reduction is expected.
Furthermore, the system can be made flexible, and the performance can be improved.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of a memory system including a memory controller according to the present invention and accessing a memory via a bus.

FIG. 2 is a more specific block diagram of the memory controller shown in FIG. 1;

FIG. 3 is a diagram illustrating an example of a conventional memory system designed to make memories mutually accessible by an architecture constructed by both Harvard and Neumann systems.

FIG. 4 is a diagram showing another example of a conventional system for enabling Harvard and Neumann mutual access.

[Explanation of symbols]

1, 41: memory a, 2, 42: memory b, 3, 30,
34: instruction memory controller, 4, 31: Neumann processor, 5, 33, 33 ': Harvard processor, 13: bank A, 14: bank B, 15, 17: memory access circuit, 16, 18: memory read / write circuit,
19 Harvard processing circuit, 20 Harvard instruction memory circuit, 21 Harvard data memory circuit, 2
2 Neumann type memory circuit, 23 Bus architecture selection circuit, 24 Bus, 25 Bus request Neuman, 26 Bus request Harvard, 32 Bus conversion block, 35 Memory controller for data, 41 '
... memory c, 42 '... memory d.

Claims (4)

[Claims] 1. A memory in a memory system configured to be able to access a memory in a memory device having a processor provided for performing an operation of an access method using a different bus architecture by a processor via a common bus. The control device corresponds to a common control means for controlling reading and writing of the memory and each access method for processing a bus input according to an access method according to the different bus architecture as an input signal to the common control means. Signal processing means, and recognition means for recognizing a difference in an access method based on the different bus architecture from a control signal generated based on securing a bus in each processor and used for controlling the memory control device itself, Depending on the recognition result of the recognition means, Selecting means for selecting the signal processing means corresponding to the access method, wherein a specific bus architecture selected from the different bus architectures is constructed by the operation of the selecting means. . 2. The method according to claim 1, wherein the bus input by the processor has a configuration of a plurality of bits, and when a plurality of memories are prepared as the memories, the plurality of memories are read and written simultaneously with each of the plurality of memories. 2. The memory control device according to claim 1, wherein a control bank as said common control means is provided, and said signal processing means corresponding to each access method corresponding to said control bank is provided. 3. The processor according to claim 1, wherein the processor is provided to construct a Neumann bus architecture and a Harvard bus architecture, and a plurality of bits constituting the bus are provided by a bus master device as the signal processing means corresponding to each access method. 3. The memory control device according to claim 2, wherein the control bank is allocated according to the bit order, and a Harvard bus architecture and a Neumann bus architecture can be constructed. 4. The memory control device according to claim 1, wherein said memory controller is operated by a bus input input via said common bus in accordance with an operation of said processor to control said memory and said different ones. A memory system capable of accessing the memory by performing an operation of an access method based on a bus architecture.