JPH0243663A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To improve the operating efficiency of a system by time-divisionally processing a processor where a fault has occurred with the other processor based on a switching signal when the fault has occurred at any one of the plural processors. CONSTITUTION:An error detecting means 101 outputs an error detecting signal when the fault is detected at any one of plural processors 110. By the error detecting signal, a switching means 102 becomes effective, and the switching signal is outputted at every prescribed time. Based on the switching signal, the other processor 110 time-sharingly processes the processor 110 where the fault has occurred. Thus, even when the fault has occurred at any one of the plural processors 110, the other processor 110 time-sharingly processes the processor 110 where the fault has occurred. Consequently, the whole multiprocessor system can continue the operation. Thus, the operating efficiency of the system can be improved.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Examples ■, Correspondence between the Examples and FIG. 1 ■ , First Example (i) Configuration of the first example (ii) Operation of the first example ■, Second Example (i) Configuration of the second example (ii) Operation of the second example ■, 3rd Example (1) Structure of the 3rd Example (ii) Operation of the 3rd Example ■, 4th Example ■, Summary of Examples ■1 Modifications of the Invention Effects of the Invention [Summary] Differentiated functions Regarding multiprocessor systems, the system is introduced from multiple processing devices that perform processing, error detection means for detecting failures that occur in any of the multiple processing devices, and error detection means for the purpose of increasing system operational efficiency. a switching means that outputs a switching signal at predetermined intervals based on an error detection signal from the plurality of processing devices, and when a failure occurs in any one of the plurality of processing devices, the other processing device outputs a switching signal based on the switching signal. The processing of the processing device in which the failure has occurred is configured to be time-divisionally processed.

[Industrial application field]

The present invention relates to a multiprocessor system in which functions are differentiated, such as a mask/slave configuration, for example.

[Prior Art] For the purpose of improving processing speed, there is a system called a multiprocessor system that includes a plurality of processing devices (processors) and constitutes a processing section of an information processing device.

In this multiprocessor system, one processor is the main processor, and other processors perform specific processing based on instructions from the main processor.
I have a system with a slave configuration.

In such a multiprocessor system, the functions of each processor are differentiated.

[Problem to be solved by the invention]

By the way, in a system where the functions of each processor are differentiated, such as the multiprocessor system with the mask/slave configuration described above, if an abnormality occurs in the operation of one processor in the system, the other processors will not function normally. Even if the system is operational, the operation of the entire system cannot be continued, resulting in a problem of poor system operation efficiency.

The present invention was created in view of these points, and an object of the present invention is to provide a multiprocessor system that improves system operational efficiency.

[Means to solve the problem]

FIG. 1 is a principle block diagram of a multiprocessor system according to the present invention.

In the figure, a plurality of processing devices 110 perform respective processing.

The error detection means 101 detects a failure occurring in any of the plurality of processing devices 110.

The switching means 102 outputs a switching signal at predetermined time intervals based on the error detection signal introduced from the error detection means 101.

Therefore, overall, when a failure occurs in any one of the plurality of processing devices 110, the other processing devices 110 are configured to time-share the processing of the failed processing device 110 based on the switching signal. Configure.

[For production]

The error detection means 101 outputs an error detection signal when detecting a failure in any of the plurality of processing devices 110. This error detection signal enables the switching means 102,
A switching signal is output at predetermined intervals. Based on this switching signal, the other processing devices 110 time-divisionally process the processing of the processing device 110 in which the failure has occurred.

In the present invention, even if a failure occurs in any of the plurality of processing units, the other processing units time-share the processing of the failed processing unit, so the multiprocessor system as a whole continues to operate. This improves the operational efficiency of the system.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of a multiprocessor system in the first embodiment of the present invention.

Here, the correspondence between I and 1 will be shown between the embodiment of the present invention and FIG.

The processing device 110 includes a mask processor 210, a slave processor 220. Bus arbiter 203° communication buffer 204. mode setting register 217a,
217b, mode control register 206. bus buffer 2
18a, 218b, extended address converter 219a,
Corresponds to 219b.

The error detection means 101 corresponds to the NOR gate 201.

The switching means 102 corresponds to the timer 202.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

1-'' (i) Configuration of the first example In FIG. 2, the multiprocessor system according to the first example includes a mask processor 210 that performs mask processing for managing the entire system, and a mask processor 21.
Slave processor 2 that performs processing based on instructions from
20, and a NOR gate 2 that detects that a failure has occurred in the mask processor 210 and the slave processor 220.
01, a timer 202 that outputs a switching signal at predetermined time intervals based on the output state of the NOR gate 201, and a communication buffer 20 that mediates the exchange of information between the mask processor 210 and the slave processor 220.
4, and a bus arbiter 203 that controls the communication buffer 204 based on a bus request signal.゛On the master processor 210 side, a memory 212 storing programs and data for mask processing and a DM are connected via a mask side bus 211.
A controller (DMAC) 213, and a floppy disk unit (FDU) 214. Hard disk device (HD
U)215. Peripheral devices such as a serial ink face 216 are connected.

On the slave processor 220 side, a slave side bus 22
1, a memory 222 storing programs and data for slave processing, a DMAC 223, and peripheral devices such as a printer 224 are connected.

Master error signal and slave error signal (mask processor 210 and slave processor 22, respectively)
If an error occurs in 0, it is set to "0'") are respectively introduced into the NOR gate 201, and the output of the NOR gate 201 is introduced into the control terminal S of the timer 202.

The timer 202 is configured to become valid and operate when "1n" is introduced to the control terminal S, and the two output terminals 01, 0! are respectively connected to the mask processor 210.
and the timer interrupt terminals T of the slave processors 220, respectively.

Here, the address space that can be accessed by the mask processor 210 and slave processor 220 is
OOOH"～°"FFFFFH"('H is 16
), which is a subscript representing a base number.

Memory 212, DMAC 213, FDU 214, H
DU215. The addresses of the serial interface 216 are “00000H” to “7” of the entire address space.
FFFFH” area.

On the other hand, the memory 222, DMAC 223, printer 2
The address of 24 is ° “80000H” ~ “F F F
F F H” Niwarisu Tochiru.

Therefore, there is no conflict between the addresses of devices, programs, and data under the control of mask processor 210 and the addresses of devices, programs, and data under control of slave processor 220.

Mask processor 210. DMAC213, slave processor 220. Bus request signals output by each DMAC 223 to request the right to use the bus are introduced into the bus arbiter 203, respectively.

The communication buffer 204 is the bus arbiter 2
Mask side bus 2 based on the direction control signal output by 03.
11 and the slave side bus 221.

Further, for example, an interrupt signal from a printer 224 under the control of the slave processor 220 is introduced to the slave processor 220 via the bus, and is also transmitted to the AND gate 220 via the communication buffer 204.
5, and the result of ANDing with the output of the NOR gate 201 is introduced into the mask processor 210.

In addition, the FDU 2 under the control of the mask processor 210
14. HDU215. Serial interface 21
Similarly, interrupt signal No. 6 (not particularly shown) is introduced into the mask processor 210 and also into the slave processor 220.

(ii) Below in 1, with reference to FIG. 2, the operation of the first embodiment will be explained separately for the case where the two processors are operating normally and the case where a failure occurs in one of them. .

(ii-1) Normal case Mask processor 210 and slave processor 22
0 are operating normally, mask processor 210 and slave processor 220 perform mask processing and slave processing, respectively.

In this case, since both the mask error signal and the slave error signal are "1", the output of the NOR gate 201 becomes ``0'', and the timer 202 does not operate, so no switching signal is output.

Further, for example, an interrupt signal from the printer 224 activates interrupt processing for the slave processor 220, but even if this interrupt signal is input to the AND gate 205, the output of the NOR gate 201 is "0", so the mask No interrupts are initiated for processor 210.

(ii-2) If a failure occurs in either one, for example,
When a failure occurs in the slave processor 220, the slave error signal becomes °0'', and the output of the NOR gate 201 becomes "1", so the timer 202 starts operating at predetermined intervals (for example, time t). A switching signal having values of "'0゛°" and "1" is output.

When the switching signal input to the timer interrupt terminal T is '0', the mask processor 210 controls the memory 212.
DMAC213, FDU214. Performs mask processing to manage the HDU 215 and serial interface 216.

When time t has elapsed, the switching signal output by timer 202 becomes "1".

At this time, the mask processor 210 saves the contents of the program counter for mask processing to a stack, etc.
On the other hand, the address of the program for the slave processing is loaded into the program counter, and the memory 222. DMAC223
and performs slave processing for managing the printer 224.

When the mask processor 210 performs slave processing, the mask processor 210 outputs a bus request signal to the memory 222 . DMAC 223° Accesses the printer 224.

In this way, based on the switching signal output from timer 202, mask processor 210 alternately performs mask processing and slave processing.

Further, when the mask processor 210 is performing slave processing, the interrupt signal of the printer 224 is sent to the AND gate 20 through the communication buffer 204.
5, interrupt processing can be activated for the mask processor 210.

Even if a failure occurs in the mask processor 210, the slave processor 220 similarly performs time-sharing processing of mask processing and slave processing, thereby allowing system operation to continue.

(2) Second Embodiment FIG. 3 is a block diagram of a multiprocessor system according to a second embodiment.

(i) In the configuration diagram of the second embodiment, the multiprocessor system according to the second embodiment is different from the multiprocessor system according to the first embodiment.
A mode setting register 217a that operates based on a slave error signal, a mode setting register 217b that operates based on a mask error signal, and a mode setting register 2
17a or a mode control register 206 that can be accessed only through the mode setting register 217b.

The master error signal and slave error signal are input to input terminals I, , I of mode control register 206.

has been introduced.

Furthermore, the output terminal 0° of the mode control register 206 is connected to the memory 212. DMAC213, FDU214, HDU2
15. It is connected to each control terminal S of the serial interface 216, and the output terminal 02 of the mode control register 206 is connected to each control terminal S of the memory 222, DMAC 223, and printer 224.

Here, the memory 212. DMAC213, FDU214
．． HDU215. Serial interface 216 and memory 222. It is assumed that the DMAC 223 printer 224 is configured so that it can be accessed by the mask processor 210 or the slave processor 220 only when the input to each control terminal S is "1".

In this case, the addresses of these memories and devices are shared by mask processor 210 and slave processor 220.
It can be placed throughout the address space handled by .

(i-2) Detailed configuration of mode control register FIG. 4 is a detailed configuration diagram of the mode control register 206 of the multiprocessor system shown in FIG. 3.

The mode control register 206 includes a Nantes gate 261,
A D-type flip-flop (D-FF) 262, a Nant gate 263, and two exclusive Noahs (EX-N)
OR) gates 264a, 264b and two OR gates 265a, 265b.

The Nante gate 261 has a mode setting register 217a.
Alternatively, an address signal and a write signal are introduced via the mode setting register 217b, and the output of the Nant gate 261 is input to the clock terminal of the D-FF 262.

One bit of input data is input to the input terminal of the D-FF 262 from the data bus.

The master error signal inputted to the input terminal It of the mode control register 206 is introduced into one input terminal of the Nant gate 263, and the master error signal inputted to the input terminal It of the mode control register 206 is introduced.
The slave error signal inputted to the input terminal I2 of the NOR gate 263 is inputted to the other input terminal of the NAND gate 263, and is inputted to one of the input terminals of each of the EX-NOR gates 264a and 264b.

Outputs from the output terminal Q and the output terminal ζ of the D-FF 262 are introduced into the other input terminals of the EX-NOR gates 264a and 264b, respectively.

The outputs of the EX-NOR gates 264a and 264b are inverted input to one of the input terminals of the OR gates 265a and 265b, respectively, and the output of the Nant gate 263 is inverted input to the other input terminal of the OR gates 265a and 265b. .

Further, in the D-FF 262, the output of the Nant gate 263 introduced to the control terminal S is "0" (that is, at least one of the mask processor 210 and slave processor 220
It is configured to be effective only when a failure occurs).

The output of the OR gate 265a is the memory 212°DMAC
213, FDU214. It is output from output terminal 01 as a mask-side enable signal that enables access to the HDU 215° serial interface 216.

The output of the OR gate 265b is the memory 222°DMAC
223 and is output from the output terminal 02 as a slave-side enable signal that enables access to the printer 224.

With reference to FIGS. 3 and 4, mode control register 206
Explain the operation.

The mode control register 20
When writing to 6, write to Nantes gate 26.
At the falling edge of the output of 1, data is written to the D-FF 262.

Based on this data, the mask error signal, and the slave error signal, the mode control register 206 outputs a mask side valid signal and a slave side valid signal as shown in the table below.

(Margin below this page) In the table, "r error signal (mask)" is the data error signal, "error signal (slave) J is the slave error signal, and r data" is the write data.

r effective signal (mask) 1 indicates a mask side effective signal, and r effective signal (slave) J indicates a slave side effective signal.

Here, if both the mask error signal and the slave error signal are turned on, the operation of the entire system becomes impossible.

(ii-2) When the overall operation is normal, both the mask-side valid signal and the slave-side valid signal become ``l'' as described above, so the mask processor 210 uses the memory 212. DMAC213, FD
U214. HDU215. The serial interface 216 is placed under management and mask processing is performed. The slave processor 220 also includes a memory 222 . DMAC22
3. Place the printer 224 under management and perform slave processing.

On the other hand, if a failure occurs in the slave processor 220, for example, the operation of the mode setting register 217a becomes valid according to the slave error signal, and the mask processor 21
Writing to the mode control register 206 is possible from 0.

When the switching signal output from the timer 202 switches to 1° while the mask processor 210 is performing mask processing, the mask processor 210 sets data "0" to the mode control register 206 via the mode setting register 217a. Write.

Due to the operation of the mode control register 206 as described above, the mask side valid signal is “0” and the slave side valid signal is “0”.
°1", the memory 212.DMAC213, FDU214.HDU215 by the mask processor 210
．． Access to serial interface 216 is no longer possible and memory 222 . DMAC22
3. Access to the printer 224 is permitted.

This causes the mask processor 210 to
The DMAC 223 and printer 224 are placed under management and slave processing is performed.

On the other hand, when the switching signal becomes "O", the mask processor 2
10 writes data "1'° to the mode control register 206 via the mode setting register 217a. As a result, the mask side valid signal becomes "1", and the mask processor 210 writes the data "1'°" to the mode control register 206 via the mode setting register 217a.
14. The HDU 215 and serial interface 216 are placed under management and mask processing is performed.

In this way, the memory and peripheral devices that can be accessed by the mask processor 210 are switched according to the mask side valid signal and the slave side valid signal output by the mode control register 206.
performs time-sharing processing of mask processing and slave processing.

(2) Third Embodiment FIG. 5 is a block diagram of a multiprocessor system according to a third embodiment.

(i) In the configuration diagram of the third embodiment, the multiprocessor system according to the third embodiment has a mask processor 210 and a memory 212 added to the multiprocessor system according to the second embodiment shown in FIG.
．． DMAC213, FDU214, HDU215.
A bus buffer 218a that mediates the exchange of information with the serial interface 216, and a slave processor 2
20 and Memo IJ 222. A path buffer 2 that mediates the exchange of information between the DMAC 223 and the printer 224
18b.

The mode control register 206 generates a mask-side valid signal and a slave-side valid signal, as in the second embodiment described above, and this mask-side valid signal is introduced into the control terminal S of the path buffer 218a, and the slave-side valid signal is introduced into the control terminal S of the path buffer 218b.

Here, the path buffer 218a, the path buffer 218b
is configured to operate only when the input to the control terminal S is "l"'.

(ii) Third operation As in the second embodiment described above, under normal conditions, both the mask side valid signal and the slave side valid signal are "1", and the mask processor 210 and the slave buffer 218
The slave processor 220 performs mask processing by controlling the memory and peripheral devices on the mask side via the slave processor 220.
performs slave processing while controlling the memory and peripheral devices on the slave side via the path buffer 218b.

For example, if a failure occurs in the slave processor 220, the mask processor 210 writes "1" to the mode control register 206 via the setting register 217a based on the switching signal from the timer 202, thereby controlling the path buffer. By operating the pass buffer 218a to perform mask processing and writing 0'' to the mode control register 206, the pass buffer 218b is operated to perform slave processing.

(2) Fourth Embodiment FIG. 6 is a block diagram of a multiprocessor system according to a fourth embodiment.

In the figure, the multiprocessor system according to the fourth embodiment has a master side bus 211 and a slave side bus 2 in addition to the multiprocessor system according to the first embodiment shown in FIG.
It is constructed by adding extended address converters 219a and 219b that extend 21 address buses by 1 bit each.

FIG. 7 shows the extended address converter 21 shown in FIG.
FIG. 9 is a configuration diagram of No. 9.

In the figure, the extended address converter 219a is composed of a register 701 and a decoder 702, and normally "0" is written in the register 701.

The extended address converter 219b is configured in a similar manner, and normally "1" is written in the register 701.

The output of the register 701 is an address bus A that extends the 20-bit address bus (AO to A1.) of the mask side bus 211 by one bit. The output will be closed.

By the way, the addresses of the memories and peripheral devices connected to the mask side bus 211 are in the area where the most significant bit of the 21-bit address space is "0'°" (that is, the extended address bus A2° is "0°"). On the other hand, the addresses of the memories and peripheral devices connected to the slave side bus 221 are assigned to an area where the most significant bit is "1°" (ie, the extended address bus A2° is "1").

Therefore, for example, if a failure occurs in the slave processor 220, the mask processor 210 writes 0'' to the extended address converter 219a to
12. DMAC213°FDU214. HDU215.
Access to the serial interface 216 becomes possible, and by writing “1”, the memory 22
2. Access to the DMAC 223 and printer 224 becomes possible.

This allows the mask processor 210 to perform time-sharing processing of mask processing and slave processing based on the switching signal.

Also, at every predetermined time t output from the timer 202,
The switching signal that takes the values of '0゛' and '1' is directly sent to register 7.
By writing to 01 and using it as an extended address bus signal, it becomes possible to switch the memory and peripheral devices that can be accessed by the mask processor 210 and perform time-sharing processing of mask processing and slave processing.

■Summary As mentioned above, it is possible to prevent conflicts between accesses to memory and peripheral devices managed by mask processing and accesses to memory and devices managed by slave processing. When the mask processor 210 starts the timer 20
Based on the switching signal from 2, mask processing and slave processing can be performed alternately.

As a result, if one of the two processors is normal, the operation of the entire system can be continued by one processor performing time-sharing processing of mask processing and slave processing.

1. In the embodiment of the present invention described above, a multiprocessor system with a mask/slave configuration consisting of two processors has been described, but the number of processors constituting the system is is not limited to two.

Also, in "!, Correspondence between Examples and Figure 1",
Although the correspondence between the present invention and the embodiments has been described, those skilled in the art will easily assume that the present invention is not limited to this and that there are various modifications.

〔Effect of the invention〕

As described above, according to the present invention, when a failure occurs in a plurality of processing devices with differentiated functions constituting a multiprocessor system, a normal processing device performs time-sharing processing of the plurality of processes, and the entire system is It is extremely useful from a practical point of view because it can be operated as a system and the operational efficiency of the system is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of a multiprocessor system according to the present invention. FIG. 2 is a block diagram of a multiprocessor system according to a first embodiment of the present invention. FIG. 3 is a diagram of a multiprocessor system according to a second embodiment. , FIG. 4 is a configuration diagram of the mode control register shown in FIG. 3, FIG. 5 is a configuration diagram of a multiprocessor system according to a third embodiment, and FIG. 6 is a configuration diagram of a multiprocessor system according to a fourth embodiment. FIG. 7 is a block diagram of the extended address converter shown in FIG. 6. In the figure, 101 is an error detection means, 102 is a switching means, 110 is a processing device, 201 is a NOR gate, 202 is a timer, 203 is a bus arbiter, 204 is a communication buffer, 205 is an AND gate, 206 is a mode control register, and 210 is a mask 211 is a mask side bus, 212.222 is a memory, 213.223 is a DMAC1, 214 is an FDU, and 215 is an HDU. 216 is a serial interface, 217 is a mode setting register, 218 is a path buffer, 219 is an extended address converter, 220 is a slave processor, 221 is a slave side bus, 224 is a printer, 261 is a Nant gate, 262 is a D-type flip-flop, 263 is a Nant gate, 264 is an exclusive NOR gate, 265 is an OR gate, 701 is a register, and 702 is a decoder. Principle 7 of the third day of drying No. 7 Part 1, 77 Figure 1 ↑ Unfinished dress concert "-l?'s Yoshizo Shunkai Pi 9 Figure 7
figure

Claims (1)

[Claims] (1) A plurality of processing devices (110) that perform processing, an error detection means (101) that detects a failure occurring in any of the plurality of processing devices (110), and introduction from the error detection means (101). Based on the error detection signal
Switching means (102) that outputs a switching signal at predetermined intervals
and, when a failure occurs in any of the plurality of processing devices (110), the other processing device (110) switches to the processing device (110) in which the failure has occurred based on the switching signal. A multiprocessor system characterized in that processing is configured to perform time-sharing processing.