JPS645341B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data processing system, and particularly to a data processing system suitable for a shared memory system of a multiprocessor system.

[Prior Art] Conventionally, each individual memory performs unique addressing, and there is never a plurality of memories with the same address. If you have multiple memories set to the same address, each memory operates independently and independently of other memories, so if you access each memory at a certain address, multiple memories will be accessed at the same time. Normal operation cannot be guaranteed because specific memory cannot be specified.

Conventionally, in a multiprocessor system consisting of multiple processors, each with its own memory,
The interface between each processor is implemented using a DMA method using registers in the middle, but in the future it is likely that a shared method will be used in which a processor directly accesses the memory of the other processor. In this case, addressing of the shared memory must be done differently, which increases the memory cost.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing system in which one processor can directly access the memory of another processor without increasing memory costs.

[Summary of the invention]

The data processing system of the present invention includes a first processor connected to a dedicated first memory;
a plurality of second processors each independent of the processor; and a second memory independent of the first memory provided corresponding to each of the second processors, the second memory being independent of the first processor and the corresponding one. The second
each second memory is configured to accept access from a corresponding second processor, and each of the second memories has its entire area as an access target for a corresponding second processor; In a data processing system in which a part of the area that can be arbitrarily set for each second processor is accessed, means is provided for each of the second memories and sets the address of each of the part of the area. and a means for comparing the address of the set area and the access address, and when the comparison results in a match, prohibiting access to the first memory and accessing a second memory to which the matching address is set. It is characterized by having a means to do so.

[Embodiments of the invention]

FIG. 1 is a block diagram of a multiprocessor showing an embodiment of the present invention.

In the multiprocessor shown in FIG. 1, three child processors LP1-LP3 are connected to a bus (GP bus) B1 of a parent processor GP via respective child memories LM1-3. Child memories LM1 to LM3 each have a capacity of about 64K bytes, of which 16K
The byte area is a shared area (the shaded area in Figure 1) that is accessible even from the parent processor. The parent memory GM has a capacity of about 1 MB and cannot be accessed from the child processors LP1 to LP3.

FIG. 2 is a related diagram of each memory shown in FIG. 1.

The parent processor GP can access all areas of the parent memory GM with 1 megabyte memory addresses. In Figure 2, the shaded area is the memory that can be accessed from the parent processor GP.
represents the area. And the parent memory GM's 0
Each child memory LM1,
2 and 3, but the problematic part is the area of the parent memory GM (indicated by a blank space) that overlaps with the shared area CO of the child memories LM1 to LM3. Both of these areas are addressable from the parent processor GP, so
When this address is duplicated, the child memory LM
It is assumed that shared areas 1 to 3 (each 16K bytes) are accessed preferentially. In other words, child memory LM
Shared areas 1 to 3 are prioritized memory, parent memory GM
The overlapping area (blank area in FIG. 2) is set as non-priority memory. However, when the parent processor GP
When an address signal is sent to read the contents of the shared area of LM1 to LM3, this address signal is also output to the parent memory GM.
Both memories (LM1, 2
or 3, and GM) will be output. In order to avoid this, the present invention provides an operation inhibit signal (LMBSY) to each child memory LM1 to LM3.
A generating circuit is provided so that the LMBSY signal is generated when the address from the parent processor GP matches the address of the shared area of the child memories LM1 to LM3. If the GM selection signal, which is the enable signal for the parent memory GM, is set to "0" when the LMBSY signal is "1", the parent memory GM will not operate, and only the child memories LM1 to LM3 will be accessed. .

In addition, as shown in FIG. 1, child memories LM1 to
The switch SW 3 is provided in order to allow the parent processor GP and the child processors LP1 to LP3 to access the child memories LM1 to LM3 in a time-sharing manner.

FIG. 3 is a related block diagram within each memory according to the operation inhibit signal.

When the shared area CO of any of the child memories LM1 to LM3 is accessed from the parent processor GP via the GP bus B1, the corresponding child memory LM1 to LM3
In the comparators 14 to 16 of the LM addresses 17 to 19, a match is found, so one of the child memory selection signals S1 to 3 becomes "1".
becomes. At the same time, open collector gate 1
One of 1 to 13 turns on and the operation inhibit signal
LMBSY is input to the parent memory GM, the gate 20 is closed, and the selection signal SG of the parent memory is set to “0”.
Make it. Therefore, when the control line (W/R) is sent from the parent processor GP, since the selection signal SG of the parent memory is "0", the flip-flop FF remains reset and the set output is becomes “0” and the parent memory GM does not operate.

In this way, according to this embodiment, the parent processor
Shared area of each child memory LM1 to LM3 seen from GP
CO has the advantage that addresses can be set within a 1 megabyte space regardless of whether the parent memory GM is implemented or not, as long as there is no address overlap between shared area COs.

Note that the present invention is not limited to a parent memory and a child memory, but can be applied by providing a priority memory and a non-priority memory among a plurality of memories.

〔Effect of the invention〕

According to the present invention, one processor can directly access the memory of another processor without increasing memory costs. Specifically, in the past, in order to prevent data collisions on the bus, it was not possible to implement memory at the same parent memory address as the shared area. For this reason, for example, in order to implement a 16K byte shared area at any address in multiple child memories, it was necessary to set an unimplemented area in units of 16K bytes at any address in the parent memory. For this reason, the parent memory itself had to be composed of 16K byte dynamic devices (DRAM), which required a considerable number of devices, leading to an increase in costs. On the other hand, in the present invention, the memory can be mounted at the same address as the shared area, so there is no need to configure the parent memory with 16K bytes of DRAM as in the conventional case, and there is no increase in cost.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a multiprocessor showing an embodiment of the present invention, FIG. 2 is a diagram related to each memory shown in FIG. 1, and FIG. 3 is related to operation inhibit signals in each memory shown in FIG. 1. FIG. GP: Parent processor, GM: Parent memory, LP1~
3: Child processor, LM1-3: Child memory,
CO: Shared area, B1: GP bus, LMBSY: Operation inhibit signal (line).

Claims (1)

[Claims] 1. A first processor connected to a dedicated first memory, a plurality of second processors each independent of the first processor, and a first processor provided corresponding to each of the second processors. a second memory independent of the memory of the second processor and adapted to accept access from the first processor and the corresponding second processor; For two processors, the entire area is to be accessed, and the first
In a data processing system in which a part of the area that can be arbitrarily set for each second processor is accessed by a processor, an address is provided for each of the second memories, and addresses of the part of the area are respectively set. means for comparing the address of the set area with an access address, and when the comparison results in a match, prohibiting access to the first memory, and accessing the second memory to which the matching address is set; A data processing system characterized in that it has a means for accessing.