JPS6242308B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory control device, and more particularly to a memory control device having partially overlapping memory areas in the same address space.

When processing a large amount of memory, a portion of it may be set as an overlapping address space. This is due to the address creation ability of the central processing unit (main control unit) that supplies addresses to memory, but due to the desire to lower costs and simplify the configuration of information processing equipment, hardware parts and the number of terminals have been reduced. This is also due to the restriction that it cannot be increased.

Conventionally, in a memory device having a read-only memory and a readable-writable memory, the read-only memory and the readable-writable memory generally overlap at least partially with respect to the same address.
In such a memory device, output from read-only memory is always enabled at duplicate addresses, and output from readable and writable memory is prohibited. As a result, the area of readable and writable memory located at the same address as the address allocated to the read-only memory cannot be used, resulting in a drawback that the amount of usable readable and writable memory is reduced. Furthermore, this drawback is caused by the inconvenience that data cannot be replaced within the memory.

An object of the present invention is to provide a memory control device that can access all memory areas without waste even if overlapping memory areas are allocated to the same address space.

The present invention uses control signals to virtually convert duplicate addresses to access the memory. In particular, even if the address supply side outputs a non-duplicate address to the memory, this is not possible. The present invention is characterized in that control is performed to convert the address into an overlapping address and supply it to the memory, and at the same time, output from one memory area at the overlapping address is prohibited.

For example, according to the present invention, a signal indicating that data is being transferred using the DMA method to a memory device comprising a readable and writable memory partially located at the same address as the address allocated to the read-only memory; A memory selection circuit receives an address signal, a signal indicating that a memory has been selected, etc. as input, and controls the data output enable signals of the two types of memories mentioned above, and a main control section that controls data transferred from another device to this memory device. The read/write memory area is located at an address that does not overlap with the read-only memory so that it can be output to the read-only memory. By having a converting circuit, a memory control device is obtained which overcomes the drawbacks of the prior art and allows economical use of memory.

Next, the configuration of the present invention will be explained using the drawings.

FIG. 1 is a diagram showing the configuration of the present invention using functional blocks. In the figure, signal a is valid when data is being transferred using the DMA method, signal b is valid when a memory is selected, signal c is valid when an address allocated to read-only memory is selected, and A memory selection circuit A that receives a data output instruction signal m from the memory and outputs a signal d that enables data output from a read-only memory and a signal e that enables data output from a readable and writable memory. is provided. Furthermore, there are readable and writable memory areas that are located at the same address as the addresses allocated to the read-only memory, and readable and writable memory areas that are located at addresses that do not match the addresses allocated to the read-only memory. An address switching signal f given from the main control unit to convert the address, and an address signal g specifying the memory address.
and an address conversion circuit B which takes the signal a as an input and produces a converted address signal h as an output. When the address for the read-only memory is specified by the signal g in this control circuit, if the signals a, b, and c are valid, output from the read-only memory is prohibited and reading and writing are possible. On the other hand, if signal b, signal c, and signal m are satisfied but signal a is not satisfied, output from the read/write memory is prohibited. Also, the signal a,
If b and c are valid and the signal i instructing to write to the memory is valid, the data is transferred to the readable and writable memory corresponding to the address allocated to the read-only memory using the DMA method, and the address switching signal is sent. At f, it is possible to move the transferred data to an address that does not match the address allocated to the read-only memory. FIG. 2 shows a diagram of this address conversion. As shown in this figure, data transferred using the DMA method is converted from address area A, which overlaps with the read-only memory ROM, to address area B of the read-write memory RAM, which does not overlap with the read-only memory, using an address switching signal as shown in this figure. becomes possible.

Next, one embodiment of the present invention will be described with reference to the drawings. Figure 3 has an address space of 64 kByte, of which read-only memory is placed in 1 kilobyte from (0000) _H to (03FF), and from (0000) _H to (03FF).
If read/write memory is located at 64 kilobytes of (FFFF) _H , that is, in the address space from (0000) _H to (03FF) _H , there will be read-only memory and read/write memory corresponding to the same address. Memory is arranged. A in FIG. 3 is an address decoder circuit, which is connected to the address signal lines A ₁₁ to _{A 15} directly provided by the main control unit and the output signal A ₁₀ ' of the address conversion circuit (this is because the read-only memory is 1k bytes). takes as input and creates a signal RSEL that becomes valid when an address included in the address space where the read-only memory is located is specified. This RSEL signal and the DMA signal, MSEL signal, and R/signal given by the main control unit are used to generate a signal RMSEL indicating that the read-only memory has been selected, a signal RMEN that enables data output from the read-only memory, and a read/write signal. signal RASEL, which memory is selected
A gate circuit that creates a signal RAEN that enables data output from a readable/writable memory and a signal MW that writes data to a readable/writable memory, and a read/write signal set to (0000) _H to (03FF) _H. Data written in DMA method to available memory (0400) _H ~ (07FF) _H
It has a flip-flop for converting the address into an address, and an address conversion circuit that determines the polarity of the address signal _A10 based on the polarity of this flip-flop. The polarity of the flip-flop is controlled by signals Set and ReSet provided by the main control section. Also, when transferring data using the DMA method, address conversion is not performed. The DMA signal given by the main control unit is a signal that is valid when data is transferred using the DMA method, and the MSEL signal is a signal that is valid when writing data to or reading data from memory. It is. The R/ signal is a signal that becomes logic "0" when data is output from the main control section, and becomes logic "1" when the main control section takes in data. From a memory device with such a configuration to another device
When transferring data using the DMA method, the main control unit writes the data to be transferred to the memory at addresses (0400) _H to (07FF) _H , and after writing the data to be transferred, inverts the flip-flop of the address conversion circuit. The data written to address (0400) _H ~ (07FF) _H is virtually reassigned to address (0000) _H ~ (03FF) _H. After this, DMA operation is started and data at addresses (0000) _H to (03FF) _H is transferred. When reading data from the memory at addresses (0000) _H to (03FF) _H , the RSEL and MSEL signals must be enabled, and the data must be read from the memory allocated to (0000) _H to (03FF) _H.
When data is transferred by DMA transfer, the DMA signal also becomes valid, so the signal RAEN that enables data output from the readable and writable memory becomes valid, and data is output to signals D ₀ to _{D 7} .
At this time, the signal RMSEL that validates the output of the read-only memory is invalid because the DMA signal is valid, and no data is output from the read-only memory. On the other hand, from another device to the main memory
When transferring data using DMA method,
(0000) _H to (03FF) When address signals A ₀ to _{A 15} are given to transfer data to address _H , the MSEL signal,
Since the DMA signal and RASEL signal are valid, a readable and writable memory is selected and R/
Since the signal is logic “0”, the signal lines D ₀ to _{D 7}
The above data is written to a predetermined address in a readable and writable memory. In this way DMA
When the data transfer according to the method is completed, the main control unit inverts the flip-flop of the address conversion circuit and transfers the addresses (0000) _H to (03FF) _H and (0400) _H to (07FF) _H.
Reassign the address to (0400) _H ~
(07FF) By generating the address included in _{the H} address, the main control unit can retrieve the data transferred using the DMA method. At this time, the RMSEL signal is invalid, the MSEL signal is valid, and the logic of the R/ signal is "1", so the RAEN signal is valid, and the readable and writable memory data is output on _D0 to _D7. Ru. As a result, overlapping memory areas can be selectively accessed as appropriate.

Note that in this embodiment, when data is transferred to another device using the DMA method, it is assumed that only one of the transfers occurs, either from the main storage device to the other device or from the other device to the main storage device, but the DMA method can be used in both directions. Even if the transfer occurs alternately for each word, it can be handled in the same way. Further, although an example using a DMA control signal has been shown, another signal may be used as the control signal.

As explained above, the present invention makes it possible to set a data buffer in a readable and writable memory located at the same address as the address allocated to the read-only memory by providing a memory selection circuit and an address conversion circuit. This has the advantage that memory can be used effectively.

[Brief explanation of the drawing]

FIG. 1 shows the structure of the present invention in a block diagram. A...Memory selection circuit, B...Address conversion circuit, a...Signal indicating that data is being transferred using DMA method, b...Signal that becomes valid when memory is selected, c...Read-only A signal indicating that an address allocated to memory has been selected, d...
Signal to enable data output from read-only memory, e...Signal to enable data output from readable/writable memory, f...Address switching signal, g...Address signal, h...After conversion address signal, i...data write instruction signal to memory, j...read-only memory selection signal,
k...Selection signal for a readable and writable memory, i...Data signal, m...Data output instruction signal from the memory. FIG. 2 is a model diagram showing the address space when operating the address switching circuit. A...A readable/writable memory area located at the same address as the address allocated to the read-only memory, B...A memory area that can be switched between A and area by operating the address switching circuit, that is, the memory of A. The data in the area can be read by operating the address switching circuit and specifying the corresponding address in the memory area B. C... An area in the address space occupied by read-only memory. FIG. 3 is a circuit diagram showing an embodiment of the present invention. SET, RESET……Address switching signal, A ₀ ~
_A15 ...Address signal, _A10 '...Address signal after conversion, DMA...Signal indicating that data is being transferred using DMA method, MSEL...Memory selection signal, R/...Indicates the direction of data. When the specified signal is logic “1”, the main control unit takes in data; when the signal is logic “0”, data is output from the main control unit.
RSEL...Signal indicating that an address allocated to read-only memory has been selected, RAEN...Data output instruction signal from readable/writable memory, RASEL...Select signal for readable/writable memory, MW... Data write instruction signal to memory, RMEN...Data output instruction signal from read-only memory, RMSEL...Read-only memory selection signal, _D0 to _D7 ...data signal, A...decoder circuit, B...reading Writable memory, C...read-only memory.

Claims (1)

[Claims] 1 Data transfer between a main memory device in which read-only memory and read-write memory are arranged in the same address space with some addresses overlapping with other devices using the direct memory access method (DMA method) In a memory control device that performs
When the main control unit requests data by specifying this duplicate address, the data in the read-only memory is output, and the DMA control unit requests data writing or reading by specifying the duplicate address. In this case, a memory selection circuit that obtains a data output signal from a read/write memory to write or read data to/from a read/write memory, an overlapping memory area, and a read-only memory are The main control unit converts the addresses of non-overlapping memory areas using signals given by the main control unit and reads out data transferred to the overlapped memory areas using the DMA method, and other functions. to the device
A memory control device characterized by having an address conversion circuit that writes data to be transferred from overlapping memory areas using a DMA method.