JPH04171549A - High speed reading method for memory system - Google Patents

Abstract

PURPOSE:To read out the data at a high speed in a memory system by increasing the width of an output bus compared with a data bus of the system. CONSTITUTION:Plural (four) memory units 3 are provided. In regard of the input/output of data of each unit 3, the data are successively inputted to the units 3 and then outputted in parallel to the output buses Q0 - Q7, Q8 - Q15, Q16 - Q23 and Q24 - Q31 respectively from the units 3. For this purpose, a switch device consisting of a NOR gate 2 and an address coder 1 is used. Thus plural units 3 can be addressed at one time and the data transfer speed is increased despite a constant access time set at each unit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of transferring data to an output device such as a CRT or a laser printer.

[Conventional technology]

Conventional digital combinators have used DMA to transfer data to output devices. but.

In this method, the number of bits of data that can be transferred at one time depends on the width of the data bus because the data bus of the combinator is used.

[Problem to be solved by the invention]

As mentioned above, the number of data bits that can be transferred at once depends on the width of the data bus, so the transfer speed also depends on the data bus.

On the other hand, due to the current increase in the degree of resolution of output devices for combiators, it has become necessary to increase the data transfer speed beyond the ability of the data/yasu.The purpose of the present invention is to solve this problem. It is.

[Means to solve the problem]

In order to solve the above problem, one aspect of the present invention is to make the combinator independent of the data bus. Provide a wider (more bits) output bus. Change the memory system accordingly.

The changes are the 7-dressing method for each memory element and the addition of a switching device between the output bus and the data bus.

This section describes mass and addressing methods. The width of the address bus is m pits, and the memory system is composed of a plurality of memory units, each of which has a Fin word. However, m)n.

When accessing the Combiator main unit, the upper address (
m−n) bits select the memory unit, and the lower n
Addressing is performed by giving bits (memory units) K, which is the same as in general memory systems.When transferring data to the primary output device, only the lower n bits are used as an address, and all memory units are selected at the same time. do.

This allows simultaneous addressing of as many words as there are memory units.

A switching device between an output bus and a data bus is composed of a switch IJ + a state buffer γ, and the like. The data bus is commonly assigned to each memory unit, and the output bus is assigned independently.

At this time, if the data bus is a bit (=1 word) and the number of memory units is b, then the output bus #ia
Select to be a bit.

[Effect]

The addressing method described above allows simultaneous addressing of multiple memory units. Additionally, this can be achieved by simply adding a signal to the conventional addressing system. Switching between the output bus and the data bus serves to widen the width of the output bus, allowing parallel reading from simultaneously addressed memory units. .

As described above, even if the access time of the memory unit is constant, the transfer speed can be increased by widening the width of the output bus.

〔Example〕

This will be explained in examples. FIG. 1 shows a memory system using the method of the invention, in which the system comprises a plurality (four in the figure) of memory units 3. A block diagram Fi for illustrating the control of an individual memory unit 3 is shown in FIG. 'IIg
This is shown in Figure 2. Each memory unit un bit (8 bits in this example) is supplied with data by a data bus DO-D7. Data input and output to each memory unit 3 are sequentially input to each memory unit 3, and outputs from each memory unit 3 are output buses Q0 to Q7*QB to Q15' q, respectively.
This is performed by a switching device composed of a NOR gate 2 and an address recorder IK so that the signals are output in parallel to Q24 to Q51. That is, the upper two bits of the m bits (M.~A1?') of the address code are input to the address recorder IK, and the NOR gates 2 are sequentially accessed to select each memory unit, and the lower address bits A0~A, is used for the address of each memory unit.

The input/output of each memory unit is switched by the signals O and J applied to the terminal OUT, and the NOR gate 2 is controlled by the signal K.

In the memory system of FIG. 1, the memory capacity of each memory unit 3 is 1 Mbyte, and access from the combinator body is via 8-bit data buses DO to D7, and 32-bit output bus Q to the output device. ~Use Qi$1. Therefore, a specific operation of the 6th order, which can obtain a transfer speed four times the normal rate at the time of output, will be explained. Switching between the data bus and output bus is done using OUTK. otrr
When = o, it becomes a data bus, and when OUT = 1, it becomes an output bus. ``W/fR signal controls writing/reading to memory, and data is read/written by giving addresses A0 to A1?.The upper two bits of the address are given to address decoder 1, and the selection signal for each memory is However, by taking OUT and NOR2, it becomes valid only when accessing the combiator main body.The remaining addresses A0 to A17 are directly connected to each memory)K
give.

Lima,! A at 70UT = 0. ~A, 9, 0UT=
1, A0 to A17 are used for addressing. Memory unit 3 is shown in FIG. This unit is selected by SEL. OUT h D o~D7 and Q0~Q7
Used for switching. 0UT=0 and DO~D2.

When OUT=1, Q0 to Q7 are used for data transfer.

Specify the data input/output direction using the beam. Ao%A1° is an address, and data input/output is performed by specifying this address.

〔Effect of the invention〕

According to the present invention, data can be read out at high speed by using an output bus that is wider than the data bus of the combinator main body. In this embodiment, the bus width is 32 bits for the output bus compared to 8 bits for the data bus, resulting in a speed four times faster.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a memory system according to an embodiment of the present invention, and FIG. 2 is a block diagram of a memory unit. 1...Address decoder, 2...NOR gate, 3
...Memory unit.

Claims (1)

[Claims] A high-speed memory system characterized in that the output bus of the memory system is wider than the data bus, and a switching device between the data bus and the output bus allows multiple memories to be called in parallel, read simultaneously, and output to the output bus. Reading method.