JPS6019534B2 - Transfer control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information transfer control device between storage areas in a storage device used in an information processing device.

Traditionally, the speed of transfer instructions is largely dependent on the performance of the storage device. Additionally, transfer instructions generally account for a high proportion of all instructions used by information processing devices, and in recent years, as storage areas in the main memory have been used as input/output buffers, the speed of transfer instructions has increased throughout the system. It has come to be greatly involved in the throughput of the world. FIG. 1 is a diagram showing the relationship between storage areas to explain the transfer operation within the storage device.
There are three storage areas: 2 and output buffer 3.

Input information from an input/output device is transferred to the input buffer 11 by an input/output command. When the input transfer is completed, the information in the input buffer 11 is transferred to the work area 12 by a transfer command, and then the information is processed using the work area 12. At this time, since the input buffer 11 is empty, the next input transfer to the input buffer 11 can be started. When the processing of information using the work area 12 is completed, the information resulting from the processing is transferred from the work area 12 to the output buffer 13 by a transfer command. Once the transfer is complete,
Output transfer from the output buffer 13 to the input/output device is started, and if the input transfer has finished during this time, the input buffer 1
1 can be transferred to the work area 12.
As described above, it can be seen that each storage area is effectively used to perform input/output operations and internal information processing in parallel, and that the transfer operation between storage areas plays an important role. Traditionally, hierarchical storage structures and various hardware buffers and registers have been used to speed up transfer operations.
Furthermore, some improvements have been made, such as speeding up control by pipeline control. In addition to the above improvements, the purpose of the present invention is to further speed up the transfer operation by focusing on the function of the transfer operation itself, and instead of transferring information from one storage area to another, the information is not transferred. An object of the present invention is to provide a transfer control device that can equivalently realize a transfer function by exchanging the addresses of storage areas themselves.

The device of the present invention includes a transmission means that directly transmits a transfer source address and a transfer destination address given from the outside, and a transfer means that uses the transfer source address given from the outside as the transfer destination address. It is characterized by comprising a switching means for switching to a transfer source address, and a selection means for selecting either one of the address transmitted by the transmission means and the output of the switching means in response to an instruction of a transfer command. shall be.

Next, the present invention will be explained with reference to the drawings. FIG. 2 is a diagram showing an information processing system showing the arrangement relationship of the present invention, and shows a storage device 1, a transfer control device 2 of the present invention, and an information processing device 3.

The information processing device 3 may include an input/output control section.
The address from the information processing device 3 is sent to the transfer control device 2 via an address line 201. The address converted by the transfer control device 2 is transferred to the storage device 1 via an address line 202.
sent to. The information processing device 3 also sends storage area designation to the transfer control device 2 via the control line 204, and
5, it is possible to issue an instruction to replace the storage area. Normally, in addition to the above-mentioned signal lines, a storage device uses control signal lines for write/output designation, write mask designation, etc., but since these are not directly related to the gist of the invention, their detailed explanation will be omitted. A storage area 21 and a storage area 22 are shown in the storage device 1, and the storage area addresses of these are now assumed to be AI and A2.

When transferring information from the storage area 21 to the storage area 22, a transfer command is usually executed, the information in the storage area 21 is read to the information processing device 3, and then the information is written from the information processing device 3 to the storage area 22. It will be done. In the present invention, when a transfer command is issued, instead of issuing a read or write instruction to the storage device 1, an instruction is sent to the address translation device 2 to exchange the storage area address AI and the storage area address A2 via the control line 204. issued through. After the replacement is performed, when the storage area address AI is output from the information processing device 3 through the address line 201, the storage area address A2 is specified to the address line 202 from the address conversion device 2, and conversely, the storage area address A2 is specified to the address line 201. When the storage area address of AI is output, the address line 202 is designated with the storage area address of AI. In this way, from the perspective of the information processing device 3, the information in the storage area 21 is transferred to the storage area 22, and conversely, the information in the storage area 22 is transferred to the storage area 21. Next, the configuration of the present invention will be explained with reference to FIG. To simplify the explanation, addresses are given as 16-bit binary numbers, with the upper 8 bits (bit 0 to bit 7) representing the storage area address, and the lower 8 bits (bit 8 to bit 15) representing the address within the storage area. Let us express the following. That is, each storage area consists of a 250-byte area represented by 8 bits of binary number, and there are 256 storage areas of 25 digits. address line 2
A 16-bit address is given to the pre-conversion address 31 through 01, of which the lower 8 bits are directly sent to the lower 8 bits of the post-conversion address 33 via line 303. The upper 8 bits of the pre-conversion address 31 are sent to the address conversion circuit 32 through a line 301, and the storage area address converted here is sent to the upper 8 bits of the post-conversion address 33 via a line 302. The converted address 33 is sent to the storage device 1 via the address line 202. In this way, the lower 8 bits, ie, the address within the storage area, are not converted, but only the upper 8 bits, ie, the storage area address, are converted. Next, a first embodiment of the present invention will be described with reference to FIG.

FIG. 4 shows a switching instruction flip-flop 41, an address switching circuit 42 of an associative memory 44, an OR circuit 43, and a selection circuit 45. The associative memory 44 is composed of 2 words x 8 bits, and is connected to a match search and write data line 301, an output data line 406, output address lines 403, 404, and match signals 401, 402. In the associative memory 44, a storage area address AI and a storage area address A2 to be converted are written in advance according to instructions from a control line 205. Storage area addresses AI and A2 can specify any one of 25 storage area addresses. When the switching instruction flip-flop 41 is at the logical 0 level (hereinafter referred to as "0"), the line 407 is "
0'' and the switching circuit is in the normal direction, that is, line 401 and line 4.
03 is connected, and wire 402 and line 404 are connected. The switching instruction flip-flop 41 is set to logical 1 level (
(hereinafter referred to as “1”), the line 407 changes to “
1" and the switching circuit is in the opposite direction, ie, line 401 and line 40.
4 is connected, and line 402 and line 403 are connected. The selection circuit 45 is a circuit that selects the replacement area address on the line 301 and the storage area address read out from the associative memory 44 on the line 406 according to the instructions on the line 405. When the line 405 is "0", the signal on the line 301 is selected, and when the line 405 is "1", the signal on the line 406 is selected. The line 405 becomes "1" when either the match signal line 401 or 402 of the associative memory 44 becomes "1" by the OR circuit 43. In other words, line 301
The storage area address sent via
2, the line 406 is selected, and if the flip-flop 41 is "0" at this time, the word of the associative memory in which the match was detected is read out through the switching circuit 42, and the flip-flop 41 is "0". 1”, the word of the associative memory for which no match was detected is read out by switching the read address of the associative memory in the switching circuit 42 and sent to the selection circuit 4.
5 to line 302. Now, if the contents of the flip-flop 41 before the transfer command is issued are "0", the storage area address AI is set to AI, and the storage area address A
2 corresponds to A2, and the storage area address has not been replaced.

The control signal line 204 is driven by the transfer command, and the flip
When the flop 41 is inverted from "0" to "1", the storage area address AI becomes A2, and the storage area address A2 becomes A2.
I, and the addresses of storage area AI and storage area A2 are exchanged. The configuration of the present invention has been described above with reference to FIG. It is possible to exchange addresses between storage areas. Next, referring to FIG. 5 showing a second embodiment of the present invention, an address conversion operation for exchanging two adjacent storage areas will be described.

The 8 bits of the converted 100 million area address sent via line 301 are the upper 7 bits (bits 0 to 6) representing the storage area group address that combines two adjacent storage areas, and the two memories in the storage area group. It is divided into lower 1 bit (bit 7) that selects one from the area, and is output to line 501 and line 502, respectively. After direct conversion, the signal on line 501 is sent to the upper 7 bits of address line 302, and the signal on line 5
The signal 02 is sent to the lower 1 bit of the address line 302 after conversion via the exclusive OR circuit 53 via the line 507.
The exclusive OR circuit 53 connects the output line 506 of the AND circuit 52
When is "1", the value on line 502 is inverted and output on line 507. When line 506 is "0", the value on line 502 is output as is on line 507. The logic neck circuit 52 has a line 503.
The value of the switching instruction flip-flop 51 is input through the line 505, and the output signal of the matching circuit 54 is input through the line 505. The register 55 is a 7-bit register, and the storage area group address to be converted is set in advance on the control line 20.
It is set by 5. Switching instruction flip-flop 51 inverts each time it is instructed by control line 204. Now, when the flip-flop 51 becomes "0", the line 503 becomes "0", and as a result, the output line 506 of the AND circuit 51 becomes "0". After the control line 204 is driven by the transfer command and the flip-flop 51 is inverted from "0" to "1", the storage area group address in the register 55, that is, the address that matches the address on the line 504 is placed on the line 501. When the output line 5 of the matching circuit 54 appears
05 becomes "1", "1" is outputted to the output line 506 of the AND circuit 52, and the least significant bit of the line 301 is inverted and outputted to the line 302. As explained above, after the transfer command is issued, the two storage areas in the storage area group specified by the register 55 are exchanged. 6th
The figure shows a third embodiment of the present invention in which a read/write memory (hereinafter referred to as RAM) 61, a selection circuit 62, and a register 6
3 and a matching circuit 64, which performs address conversion between four adjacent storage areas. The 8 bits of the converted 100 million area address sent by the address line 301 include the upper 6 bits (bits 0 to 5) representing the storage area group address that combines four adjacent storage areas, and the four upper bits in the storage area group. It is divided into two lower bits (bit 6 and bit 7) that specify one of the storage areas, each connected to line 601.
is output on line 602. The RAM 61 is composed of 4 words x 2 bits, and is a circuit for converting the lower two bits of the address line 301. The 2 bits on line 602 are supplied to RAM 61 as the input address, and the 2 bit converted address is read out on line 603 from the corresponding word.
In this embodiment, the control line 204 from the information processing device consists of 5 bits, and is divided into RAM61 write data 607 (2 bits), RAM61 write command 608 (1 bit), and RAM61 write address 609 (2 bits). be done. Before conversion, the first word of the RAM 61 is set to 00 by the control line 204, and the second word is 01.
, the third word ``10'' and the fourth word ``11'' are written, and the contents correspond to the proposed address falling on the line 602. It can be seen that if an address of 01 is given to line 602, the second word is selected and 01 is read out to line 603, indicating that no conversion is performed. register 63
The matching circuit 64 is a circuit for specifying a storage area group to be converted.
05 to set the address A of the storage area group to be converted. When a match between the lines 601 and 604 is detected, the output line 605 of the match detection circuit 64 becomes "1", and the selection circuit 62 selects the line 603. The upper 6 bits of the pre-conversion address given by line 301, that is, the storage area group address, are directly supplied to the post-conversion address line 302 via line 601, and the lower 2 bits are set to "0" on line 605.
When , the signal on line 602 is “1”, and when line 605 is “1”, the signal on line 603 is sent to line 3 via selection circuit 62 and line 606.
It is supplied to the lower two bits of the 02 signal. Now, suppose that a transfer command is issued between the second storage area and the third storage area in the storage area group. Information processing equipment first goes to line 2
04 sets the second word of RAM 61 to 01). et al.1
Then, the third word of RAM61 is rewritten from 10 to 01. This means that the transfer command is completed, and from then on, the storage area group address A appears on line 301, and when the storage area address in the storage area group is 01, it is converted to 10, and when it is 10, it is converted to 01. address is line 302
It will be output and replaced. As described above, the present invention has been explained using three embodiments, and it can be seen that the designation of the storage area and the instruction to replace the storage area address are appropriately performed.

Due to its principle, the transfer control device according to the present invention inevitably performs back transfer from the transfer destination to the transfer source at the same time as transfer from the transfer source to the transfer destination, so if back transfer is inconvenient, for example, If it is desired to initialize the entire storage device with the same pattern using a transfer command, a conventional transfer command is also required.

For this reason, it is effective to use the present invention in coexistence with conventional transfer commands depending on how the transfer commands are used, rather than subjecting all transfer commands to transfer control as in the present invention. As described above, the present invention is a device that can specify the address of a storage area to be migrated, and has the advantage that migration can be instantaneously realized by exchanging the addresses of the storage areas.

Furthermore, since the speed of the migration control according to the present invention does not depend on the size of the storage area, it can be said that the larger the storage area to be migrated, the greater the effect. Brief explanation of drawings 1st
The figure is a diagram showing the relationship of storage areas to explain the transfer operation within the storage device, FIG. 2 is a configuration diagram of the device system showing the arrangement relationship of the present invention, and FIG. 3 is a block diagram of the configuration of the present invention. Figure 4 shows the address conversion circuit 3 shown in Figure 3.
2, FIG. 5 is a circuit diagram showing a second embodiment of the address conversion circuit 32 shown in FIG. 3, and FIG. 6 is a circuit diagram showing the address conversion circuit 32 shown in FIG. 3. circuit 332
FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

In FIGS. 1 to 6, 1... storage device;
2...Address translation device, 3...Information processing device, 31...Address before conversion, 32...
... Address conversion circuit, 33 ... Address after conversion, 41, 51 ... Switching instruction flip-flop, 42 ... Switching circuit, 43 ... Logic sum circuit, 44... associative memory,
45,62...Selection circuit, 55,663...
...Register circuit, 54, 64...Coincidence detection circuit, 52...Logic bond circuit, 53...Exclusive OR circuit, 61...Read/ write memory.

Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1 A transmission means that transmits the transfer source address and transfer destination address given from the outside as they are, and a transfer source address given from the outside as the transfer destination address and the transfer destination address given from the outside as the transfer source address. A transfer control device comprising: switching means for switching to: and selection means for selecting either the address transmitted by the transmission means or the output of the switching means in response to a transfer command instruction. .