JPS60254477A - Memory system - Google Patents

Abstract

PURPOSE:To access a word at a high speed from an optional bit in the word by providing a data rotation means between a work bit array matching with a memory and a word bit array matching with a data transfer means. CONSTITUTION:Bit inputs and bit outputs of each chip are connected to a data bus 12 through a data rotation circuit 11 in parallel. The data rotation circuit 11 is connected to a control circuit 14 which generates an output according to the data of a control register 13, and makes mutual alterations determined according to the output of the control circuit 14 between the word bit array matching with the memory 10 and the word bit array matching with the word bit array of the data bus 12. Consequently, a word in the memory is accessed as if there were no boundary of words, and the access is attained at a high speed as compared with conventional software processings.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field of the Invention The present invention relates to a memory system, and more particularly to a memory system in which access is performed in word units and words can be accessed from arbitrary bits within the access word.

(0) Background of the Technology Data handled by information processing devices has changed from the conventional code data format to include bit data formats such as image data.

Since conventional storage devices are not configured to be able to immediately respond to such diversification of data formats, there is a demand for the development of technical means that can solve this problem.

(C) Prior Art and Problems Conventional memories can be accessed in units of a predetermined data length, for example, in words.

Therefore, as long as data in such a code data format is handled, no inconvenience will occur.

However, when attempting to use the above-mentioned type of memory to handle bit data such as image data, the atlus boundary becomes a major obstacle, making it impossible to store words from an arbitrary focus position. Although software processing is one way to avoid such problems, it has the disadvantage that the processing time becomes longer and the access speed is noticeably lowered.

<,-) Purpose of the Invention The present invention has been made in view of the above-mentioned drawbacks of the prior art, and its purpose is to access a word at high speed from an arbitrary hint within the word to be accessed. The goal is to provide a memory system that can

(E) Structure of the Invention In order to achieve this object, the system of the present invention includes a memory in which a word consisting of a plurality of hits is accessed by access means for each bit, and a means for transmitting and receiving data between the memory. , word address supply means, address correction means connected to the word address supply means for modifying the word address to the next word address, and arbitrary access to the word specified by the word address issued by the word address supply means. control means for specifying a start bit; and an address multiplexer for supplying the outputs of the address supply means and the address modification means to the memory access means determined in accordance with the outputs of the control means;
A device is provided between the memory and the data exchange means, and causes a mutual change determined in accordance with the output of the control means between a word bit array adapted to the memory and a word hit array adapted to the data exchange means. The system is configured to include a data rotation means for closing the data.

Embodiments of the Invention The present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 shows an embodiment of the invention. In this figure, 1
0 is memory, and an example of the configuration of this memory is 1 Hiso 1
-XN chips, and the bit input and bit output of each chip are connected in parallel to a data bus 12 via a data rotation path circuit 11. The data rotation buffer circuit 11 is a control circuit I that generates an output according to the data of the control register 13.
4 for producing a mutual change between the word bit arrangement adapted to the memory 10 and the word bit arrangement adapted to the word bit arrangement on the data bus 12, which is dependent on the output of the control circuit 14. It is something.

Furthermore, the addressing units 10oo, 10n, . . . 1077 of each chip 10o . . . 107 of the memory 10 have corresponding address multiplex circuits 15o .
connected to the output of The outputs of the address bus 16 and the address modification circuit 17 are connected to two address inputs of these address multiplex circuits 15o...157, respectively, and the control inputs of the control circuit 1
The address multiplex circuits 15o to 157 are connected to the outputs of the address bus 16 and the address correction circuit 17, and send the outputs of the address bus 16 and the address correction circuit 17 to the addressing section of the memory 1 determined according to the output of the control circuit 14. There is. The address correction circuit 17 outputs an address that is 1 larger than the address on the address bus 7.

Next, the operation of the system of the present invention having the above configuration will be explained.

For convenience of explanation, an example (see FIG. 2) will be described in which a word on data bus 12, for example, an 8-bit byte, is written from bit 6 of address #2 to bit 5 of address #3 of memory 10.

Address data specifying address #2 of memory 10 is applied to address bus 16, and data specifying bit 6 thereof is sent to control register 13. From the control circuit 14 responsive to data in the control register 13,
The bytes that are about to be written are the 6th and 7th memory byte locations specified by address data, and the 0th to 5th memory byte locations specified by address data that is 1 larger than the above address data. A signal indicating that the data is to be written to the address multiplex circuit L5o...151 is supplied to the data rotation buffer circuit 11.

Then, the address multiplex circuits 15s and 1
5-1, the address data on the address bus 16 is supplied to the addressing units 1066 and 10T7 of the chips 106 and 101, whereas the address multiplex circuits 15o...
The output addresses of the chips 10o...105 are supplied to the addressing units 10oo...105g of the chips 10o...105, while the data rotation circuit 11 that receives the above signal outputs the third
Each bit of the data rotated as shown in the figure is supplied to the write input of the corresponding chip.

Therefore, bits A and B of the written data are in bit positions 6 and 7 of address #2, and bits C through H
are in bit positions 0-5 of address #3.

The addressing function in reading bytes written in this way is produced in exactly the same way, but the bits CDEFGHAB constituting the byte to be read are changed to a byte consisting of bits ABCDEFGH by the reverse operation of the data rotation bar circuit 11. It is restored and sent onto the data bus 12.

In the above embodiment, an example in which an address multiplex circuit is provided for each chip has been described, but each chip is provided with an address register, and the output of the address bus 16 or the address correction circuit 17 is sent to these address registers as described above. A single circuit may be provided and configured that can be distributed to perform similar functions.

()) Effects of the Invention As is clear from the above description, according to the present invention, it is possible to (1) access words to memory as if there were no word boundaries, and (2) perform the access using conventional software processing. Effects such as being able to perform the process at a higher speed compared to the previous one can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are diagrams explaining the operation of the embodiment shown in FIG. -10 in the figure is memory, 10o...No. 107, memo 1
Chips 7, 1000, . . . , 1071, which constitute the month O, are an addressing section, 11 is a data rotation buffer circuit, 12 is a data node, 134 is a control register, 1
4 is a control circuit, 150 to 157 are address multiplex circuits, 16 is an address bus, and 17 is an address modification circuit. Figure 2 Figure 3

Claims (1)

[Claims] A memory in which a word consisting of a plurality of four bits is accessed by access means for each bit, a means for transmitting and receiving data between the memory, a word address supply means, and a word address supply means connected to the word address supply means. address modification means for modifying an address to the next word address; control means for designating an arbitrary access start bit of the word specified by the word address issued by the word address supply means; the address supply means and the address modification means. an address multiplexer for supplying the output of the above to the memory access means determined according to the output of the control means, and a word bit array suitable for the memory and the data exchange, provided between the memory and the data exchange means. A memory system comprising data rotation means for producing a mutual change between a word bit arrangement adapted to the means and a mutual change determined in dependence on the output of said control means.