JPS58218091A - Data transfer system - Google Patents

Abstract

PURPOSE:To attain totally and minutely data transfer at high speed, in such a way that byte or word transfer of high speed is done for data in matching with the boundary of byte or word and minute bit transfer is done automatically for the data not matched, by designating the address of transfer, sizes x, y of transfer area, and address to be transferred. CONSTITUTION:The length toward the (x) direction of an area of a memory where a transfer data is stored is set to a transfer area size (x) register 2, the length toward the (y) direction is set to a transfer area size (y) register 3 in advance, and further the address of storage area of a memory to be transferred is set in a transferred address register 4 in advance. In starting the system, the content of the transfer address register 1, that of a transfer area size (x) register 2, and that of a transferred address register 4 are set to a transfer circuit 9 of data toward the (x) direction in one row and the starting is done. The transfer circuit 9 toward the (x) direction in one row transfers the data toward the (x) direction in one row to a memory area from the address represented with the transferred address register 4, based on the content of the transferred address register 1 and the content of a transfer area size (x) register 2.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is based on a memory having a memory control circuit that can switch between reading and writing in byte or word units and reading and writing in bit units using a signal line. -Relates to a data transfer method that can transfer data in a memory area with size "*yt" to a certain memory area at high speed.

[Prior art and problems]

Conventional memory-to-memory data transfer circuits transfer data in byte units, word units, or bit units. In the first two cases, the transfer speed is fast: 1. Even if the data is smaller than one unit, it can only be transferred in units of units or units of words;

In the latter case, fine-grained transfer is possible (1':5), but data that can be transferred in bytes or words can only be transferred in units of focus, and the transfer speed is slow. be.

[Purpose of the invention]

The present invention eliminates the above-mentioned drawbacks, and provides a data transfer method that can transfer data in a memory area having arbitrary bit sizes x and yf to a certain memory area in a fine-grained manner and at high speed. This is the entire purpose.

[Structure of the invention]

For this purpose, the data transfer method of the present invention allows arbitrary bits and
In a data transfer method in which data in a memory area having size x and yf is transferred to a memory area where data is set to 1, there is a transfer source address register in which address information of the transfer source data storage area is set, and the data storage area is a transfer area size X register in which the size in the X direction is set;
In the y direction of the data storage area a, the transfer area size register pl,'l, where the size is set, and the transfer destination address where the address information of the data storage area of the transfer destination is set, 41-1. register, X-direction column data transfer circuit, and X-direction
A transfer source address calculation circuit that calculates the next transfer address of the transfer source based on an end signal indicating the end of data transfer of a column and updates the contents of the above transfer source address register; A transfer destination address calculation circuit that calculates the next transfer address and updates the contents of the transfer destination address register, and a register decrement circuit that subtracts the contents of the transfer area size y register based on the end signal. The X-direction-column data transfer circuit has the transfer destination address register and the transfer range size X.
Based on the contents of the register, the transfer mode of data in the X direction and column is divided into a bit transfer part and a byte or word transfer part, and the above transfer source address and address are set according to the transfer mode.
Transfer data of the size specified by the contents of the transfer area size At the same time, when the transfer of the data of the contents of the transfer area size It is characterized by being configured as follows.

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing a detailed example of the X-direction-column data transfer circuit shown in FIG. In the figure, 1 and 14 are transfer source address registers, 2 is a transfer area size X register, 3 is a transfer area size y register, 4 and 10 are transfer destination address registers, 5 is a control circuit for all circuits, and 6 and 8 are Address calculation circuit, 7 is register decrement circuit, 9
11 is a transfer destination address register increment circuit, 12 is a transfer bit number register, 13 is a transfer bit number register decrement circuit, 15 is a transfer source address register increment circuit, 16 is an address bus control circuit, 17 is a transfer mode signal line control circuit, 18 is a memory control circuit, 19 is a memory, and 2011-1' shows all data bus control circuits.

Figure 1e: First, set the starting address in the memory where the transfer data is stored in the transfer source address register in advance, and also set the length in the X direction of the area on the memory where the transfer data is stored. is set in the transfer area size do. When activated thereafter, the contents of the transfer source address register, the contents of the transfer area size The X-direction-column data transfer circuit 9 transfers the X-direction-column data to the transfer destination column based on the contents of the transfer source address register and the contents of the transfer area size X register 2. °″”゛.

Transfer to memory area. When the data transfer in the X direction column is completed, a completion signal is sent from the transfer circuit 9 for the data in the X column to the address calculation circuits 6 and 8 and the register decrement circuit 7.

In response to this end signal, the address calculation circuit 6 calculates the next transfer source address and sets the calculated address in the transfer source address register 1, and the address calculation circuit 8 calculates the next transfer destination address and sets the calculated address in the transfer source address register 1. Set the address in transfer destination address register 4, and register
The decrement circuit 7 subtracts the contents of the transfer area size y register 3 by 1. Then, the X direction-column data transfer circuit 9 is activated again. This process is repeated, and when the contents of the transfer area size y register 3 become 10'', the transfer source address register 1 and the transfer area size ((x register 2 and the data set in the transfer area size y register 3) are initialized. Transfer ends.

Next, a detailed example of the X direction-column data transfer circuit 9 will be explained in the second section.
This will be explained using figures. In Figure 2, the forwarding address and
The data of the transfer destination address register 4 shown in FIG. 1 is set in the register 10, the data of the transfer area size Similarly, the data in the transfer source address register 1 is set. X
When the direction-column data transfer circuit 9 is activated, it sends the contents of the transfer destination address register 10 through the address bus control circuit 16 onto the address bus. In the transfer mode signal line control circuit 17, if the bit address part of the contents of the transfer destination address register 10 is not "0",
For example, if the bit address field is "110", a bit mode signal is sent onto the transfer mode signal line.

Further, the transfer mode signal line control circuit 17 sends a bit mode signal onto the transfer mode signal line even when the contents of the transfer bit number register 12 become smaller than a byte or a word. In cases other than the case of transmitting a bit mode signal as described above, the transfer mode signal line control circuit 17 transmits a byte mode signal or a word mode signal onto the transfer mode signal line. When primarily transferring bytes in this way, the contents of the transfer destination address register 10 are checked, and bits that do not fit the byte boundary, that is, the first remainder, are transferred, and bits that fit the byte boundary are transferred. Transfer byte from , check the contents of the transfer bit number register 12, and if less than 1 byte of data remains at the end of the byte transfer, transfer the remaining part to a transfer device that performs bit transfer. A signal is sent from the transfer mode signal line control circuit 17 onto the transfer mode signal line.

The contents of the transfer mode are as follows: from the transfer mode signal line control circuit 17 to the memory control circuit 18, the transfer destination address register increment circuit 10, the transfer bit number register decrement circuit 13, and the transfer source address register increment circuit 15. Each person will be notified. The memory control circuit 18 selects one bit from the address on the memory 19 indicated by the contents of the transfer source address register 14 according to the transfer mode sent from the transfer mode signal line control circuit 17 when the transfer mode is bit mode. data, or in byte (word) mode, 1 byte (
word) data is sent onto the data bus through the data bus control circuit 20. The transfer destination address register increment circuit 11 increments the transfer mode signal line control circuit 17 regarding the contents of the transfer destination address register 10.
According to the transfer mode sent from the transfer mode, bit increment is performed when the transfer mode is bit mode, and byte (word) increment is performed when the transfer mode is byte (word) mode. The transfer source address register increment circuit 5.15 similarly increments the contents of the transfer source address register 14 by bit or byte according to the transfer mode sent from the transfer mode signal line control circuit 17. , word increment. Transfer bit number register
The decrement circuit 13 similarly performs bit decrement, byte decrement, or word decrement on the contents of the transfer bit number register 12 according to the transfer mode sent from the transfer mode signal line control circuit 17. By repeating the above process □, when the contents of transfer 1'□::pit number register month 21- become "0", the data transfer in the X direction-column is completed and the data is transferred as shown in Figure 1. An end signal is sent to the address calculation circuits 6 and 8 and the register decrement circuit 7.

Fig. 3 is a diagram conceptually showing the relationship between the transfer source memory and the transfer destination memory, Fig. 4 is a diagram showing the division of the data storage area of the transfer destination memory, and Fig. 5 is a diagram showing the transfer destination address register. It is a figure showing an example of a composition.

In the figure, 21 is a transfer destination memory, 22 is a transfer source data storage area, 23 is a transfer destination data storage area 24 is a bit transfer area, and 25 is a byte word transfer area. In the present invention, a memory 9 and a transfer destination memory 2 are shown in FIG.
1 is an address attached to each bit, and can be applied to the case of data transfer from the data storage area 22 of the transfer source to the data storage area 23 of the transfer destination in the same memory. Transfer 11 Addresses X and y of the original data storage area 22 are set in the transfer source address register, transfer area size x4 register 2, and transfer area size yV::1.:1° register 3 shown in FIG. 1, respectively. This is the content to be sent to the transfer destination address register 4 shown in FIG. 1. As shown in FIG.
Set to register 1. As mentioned above, the contents of the transfer mode signal line control circuit 1 shown in FIG.
7 to transfer data to the bit transfer area 24, in bit mode, and byte transfer area 2.
5, the data is controlled to be transferred in byte mode.

As described above, since the present invention transfers data having bit addresses, it is particularly effective in transferring all data for image processing.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, by specifying the transfer source address, the size of the transfer area Z4, the transfer destination address, any bit size can be set.
For data in the memory area held in '/, data that matches byte or word boundaries automatically undergoes high-speed byte transfer or 4-word transfer, and other areas undergo fine-grained bit transfer, and This has the effect of allowing detailed and high-speed data transfer.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing a detailed example of the data transfer circuit in the X direction and column shown in FIG. A diagram conceptually showing the relationship between the memory and the transfer destination memory, FIG. 4 is a diagram showing the division of the data storage area of the transfer destination memory, and FIG. 5 is a diagram showing an example of the configuration of the transfer destination address register. Demeru. 1 and 14...Transfer source address register, 2...Transfer area size X register, 3...Transfer area size y register, 4 and 10...-Transfer destination address register, 5... Control circuit for all circuits, 6 and 8... Address calculation circuit, 7... Register decrement circuit, 9...
・X direction-column data transfer circuit, 11... Transfer destination address register increment circuit, 12... Transfer bit number register, 13... Transfer bit number register decrement circuit, 15... Transfer Original address register increment circuit, 16... Address bus control circuit, 17... Transfer mode signal line control circuit, 18
...Memory control circuit, 19...Memory, 20...
Data bus control circuit, 21... Transfer destination memory, 2
2... Data storage area of the transfer source, 23... Data storage area of the transfer destination, 24... Bit transfer area, 25...
-Byte transfer area. Patent Applicant: Fujitsu Limited Representative Patent Attorney Yotsube Kyotani

Claims (1)

[Claims] In a data transfer method that transfers data in a memory area with arbitrary bit sizes x and yk to a certain memory area, there is a transfer source address register in which address information of the transfer source data storage area is set, and the above data. A transfer area size The next transfer address of the transfer source is calculated based on the transfer destination address register, the data transfer cycle in the X direction and column, and the end signal indicating the end of data transfer in the direction and column, and the above transfer is performed. Update the contents of the original address register! a transfer source address calculation circuit that calculates the next transfer address of the transfer destination based on the end signal and updates the contents of the transfer destination address register; and the end signal. and a register decrement circuit that subtracts the contents of the transfer area size y register based on the transfer area size y register. The transfer mode of data in the X direction and column is divided into a bit transfer part and a byte or word transfer part, and according to the transfer mode, data is transferred from the memory address specified by the contents of the transfer source address register to the transfer destination address register. Transfers the data of the size specified by the contents of the transfer area size X register to the memory address specified by the contents of , and
When the transfer of the data of the contents of the transfer area size X register is completed, the end signal is generated and sent to the transfer source address calculation circuit, the transfer destination address calculation circuit, and the register decrement circuit. A data transfer method featuring a unique structure.