JPS61296438A - Data parity storing system - Google Patents

Abstract

PURPOSE:To reduce the number of parity RAMs and the price of hardware by making all the parities of byte data in a data static RAM (DRAM) corre spond to bits in a parity DRAM at the rate of 1 to 1 to transfer and store an image. CONSTITUTION:When a 16-bit address signal 12 is '0', an effective chip select signal 14 is outputted. When a two-way data signal 19 is inputted, a parity signal 26 is outputted, and when a parity memory reading signal 23 is outputted at the rise of a write signal 21, a parity signal group 25 is read out from a parity DRAM 6. The signal group 25 is held by a holding circuit 7 by the write start specification of a clock signal 22, a read parity holding signal group 28 is outputted from the circuit 7, the signal 23 is invalidated, a parity writing signal 24 is validated, and a parity signal 26 is inserted into the least significant bit of the signal group 28 to output the inserted signal as the signal group 25. The corrected signal group 25 is written in the DRAM 6 and the write signal 24 is invalidated by the completion specification of a leading edge point of the signal 22 to end the storage of the data parity.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to data parity storage systems, and more particularly to data parity storage systems in static random access memories that include sensitive data bits at one address.

[Conventional technology]

Conventionally, this type of data parity storage method consists of a data random access memory for storing data, and a data parity memory for storing data.
A circuit T consisting of a random access memory for parity that stores bit parity and includes a plurality of bits at one address, a bit or one bit of parity at an arbitrary address of the random access memory for parity, and the remaining unused bits. It consists of bits and is synchronized with an externally given memo 1.1, and the data is stored in a random access memory for data, and a 1-bit parity is stored in a random access memory for parity. was.

[The problem that the invention attempts to solve]

In the conventional data parity storage method described above, since there are many unused bits in the parity random access memory that stores data parity, it is not necessary to use a large amount of random access memory, and it is difficult to implement random access memory for the same capacity. The disadvantage is that the area increases and the hardware price increases.

[Means for solving problems]

The data parity storage method of the present invention includes a parity random access memory that stores multiple bits of data parity in one address, and a data random access memory that stores data using the data parity random access memory at an address. means for one-to-one mapping to one bit in the memory; means for allocating the data parity to all the plurality of bits at a certain address in the parity random access memory; and another parity bit at the same address as the one bit parity. and means for storing the 1-bit parity from the table in the parity random access memory.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the data parity storage method of the present invention, FIG. 2 is a time chart showing an example of the harness bit storage operation in FIG. 1, and FIG. 3 is a block diagram showing an example of the data parity storage method in FIG. It is a figure which shows the mapping example.

In FIG.
．． Static random access memory for data 2 to 3. Parity bit generation circuit 4° timing control circuit 5. Static random access memory for parity 6
, holding circuit 7. Lower address decoder 8. It consists of gated buffers 9, 10°11.

Next, the operation of storing the parity of address 0 will be explained.

16-bit address signal 12 indicates address @O1,
When the upper 3 bits of the address are input to the upper address decoder 1, the upper address decoder 1 decodes and outputs the eight chip select signals 13. Depending on the 0 address specification, only the chip select signal 14 is valid. It is output to static random access memory 2. Next, the data to be stored in the static random access memory 2 for data is placed on the 8-bit bidirectional data signal 19, and the data to be stored is transferred to the static random access memory 2 for data by the memory write designation of the memory write signal 21. It is stored in Mesori 2. Seven-
When the data to be stored is input to the parity bit generation circuit 4, the parity bit generation circuit 4 calculates the parity of the data to be stored and outputs a 1 validity signal 26.

At the same time, the memory write designation of the memory write signal 21 and the memory write signal 4
When the MHz square wave clock signal 22 is input to the timing control circuit 5, the timing tII control circuit 5L outputs a parity memory read signal 23 to the parity static random access memory 6, followed by a parity memory write signal 24. . This parity memory read signal 23 outputs an 8-bit parity signal 25 from the static random access memory 6 for parity to the holding circuit 7, and the holding circuit 7 receives the 8-bit parity signal 25 at the end of the validity instruction of the parity memory read signal 23. 25 and sends the parity signal 28 to the gated buffer 10.
Output to.

When the gate control signal 27 is applied to the lower 3-bit address decoder 8 and the gated buffers 9 and 10, the 1-bit parity signal 26 of the bidirectional data signal 19 is A parity data signal 29 is output after being modified by replacing the lower bits. The parity data signal 29 that is modified by the parity memory write signal 24 and passed through the gate of the gated buffer 11 is sent to the parity static random access memory 6 with only the least significant bit modified.
is stored as.

In FIG. 1, reference numeral 15 is a chip select signal that becomes valid by specifying the FFFF address among the chip select signals 13, 16 is an address signal % that collects the 13 bits from the lowest order, and 17 is the 13 bits from the highest order. 20 is a memory read signal; 2 is a memory read signal;
7 is a gate control signal decoded by the lower address decoder 8.

Next, in Figure A2, when the 16-bit address signal 12 comes to "Ol", the chip select signal 1 becomes effective immediately.
4 is output. Subsequently, when the bidirectional data signal 19 comes, the parity signal 26 of the bidirectional data signal 19 is immediately activated.
(shown in FIG. 1) is output. Memory write signal 21
When the parity memory read signal 23 is output at a high rising point, the parity signal group 25a is read out from the parity static random access memory 6 (shown in FIG. In response to the writing start designation at point B, the read parity holding signal group 28b held in the holding circuit 7 (shown in FIG. 1) is output, invalidating the parity memory read signal 23 that was valid, and outputting the parity memory write signal. 24 and inserts the parity signal 26 into the least significant bit of the read parity holding signal group 28I].
Output to 5b. parity memory s p by signal 24
This corrected convolutional parity signal group 25b is loaded into the static random access memory 6 for parity, and then when the rise of the square wave clock signal 22 corresponds to the writing completion designation of point υ, l:jsl parity memory writing is performed. The signal 24 is invalidated and data parity storage is completed.

Next, Figure 3 shows a 64 kilobyte capacity D-Yuzuki static random access memory (hereinafter referred to as DRAM) 30
The byte data of each address is stored in a parity static random access memory (PR
AM) 31 shows an example of mapping. That is, D.R.
P the parity of the byte data at address 0 of AM30.
Map to the least significant bit of address O in RAM 31, DR
AM30 address 1, 2. The parity of the byte data of ~7 is sequentially stored at the second address of address 0 of the PRAM 31.

The third 7th to most significant bits are mapped, and the following are sequentially mapped to the address FFFF of the DRAM 30, and the entire parity of 64 kilobytes of the DRAM 30 is P.
The data is mapped one-to-one to all 8 kilobyte bits of the RAM 31 and stored in the PRAM 31.

〔Effect of the invention〕

As explained above, the present invention (1) is to map and store all the parities of the byte data of the static random access memory for data in a one-to-one correspondence with the bits of the static random access memory for parity.
Since the quantity of data parity random access memories can be reduced and the packaging density relative to the random access memory capacity can be increased, hardware costs can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the data parity storage method of the present invention, FIG. 2 is a time chart showing an example of the parity bit storage operation in FIG. 1, and FIG. 3 is a block diagram showing an example of the data parity storage method of the invention. FIG. 6 is a diagram showing an example of parity mapping.

Claims (1)

[Claims] A parity random access memory that includes multiple bits in one address and stores data parity, and a data parity of an address of a data random access memory that stores data one to one for one bit of the parity random access memory. means for mapping the data parity to all of a plurality of bits of an address in the random access memory for parity; and means for storing data in the parity random access memory.