JPH02226433A - Parity check system - Google Patents

Abstract

PURPOSE:To reduce the number of memory elements, to miniaturize a device and reduce cost by using the memory element having plural bits per word for a memory for parity bit. CONSTITUTION:An inspection means 6 odd number-inspects a having read data word and the parity bits which an extraction means 5 has extracted. At the time of write-accessing, a generation means 7 generates the parity bits from write data into a data memory 1, and a write means 8 writes the parity bits from the generation means 7 in the designated bit position which a designation means 4 has designated, and writes bits from a read means 3 in the other bit positions in a parity memory 2. Thus, the memory for parity bit can be constituted of the memory elements in which one word has plural bits, and the number of the memory elements for party bit can be reduced.

Description

[Detailed Description of the Invention] [Required 1] An object of the present invention is to provide an odd-even check method that can reduce the number of memory elements for parity bits with respect to data parity check and parity bit generation. a parity memory comprising a memory element having a plurality of bits, each bit storing a parity bit of one data word of the data memory; means for reading one word of the data word, means for specifying a parity bit position for the data word based on the address information, and extracting a parity bit from the one word read by the reading means based on the specification of the specifying means. means for performing an odd-even check on the read data word and the parity bit extracted by the extracting means during a read access; means for creating a parity bit from data written to the data memory; and during a write access;
Means is provided for writing into the parity memory the parity bit created by the creation means at the bit position designated by the designation means, and the bit successively read out by the reading means at other bit positions, and an odd-even check is performed. Configure it to do this.

[Industrial application field]

The present invention relates to parity checking of data and generation of parity bits.

2. Description of the Related Art In recent years, in information processing equipment, a method of increasing the reliability of data by adding a parity bit to memory data and performing an odd-even test has been widely used. In addition, with the demand for increased processing capabilities and performance in various computer systems, the amount of built-in programs is increasing, and along with advances in semiconductor technology resulting in lower prices for memory elements, computers are increasingly using large-capacity memories. They tend to be implemented in systems.

Therefore, it is desired to reduce the number of memory elements for parity bits, which increase with the increase in memory capacity, and the space for their implementation.

[Conventional technology]

FIG. 3 shows a memory configuration of a conventional example. The same reference numerals indicate the same objects throughout the figures.

Conventionally, for example, when the unit of memory capacity is 16K (K=1024) data words, one data word is 8 bits, and one parity bit I is added to one data word, 1
A data memory was constructed with eight memory elements each having a word of 16 bits, and a parity memory was constructed with one memory element of the same type. Therefore, a memory having a capacity of 64 data words consists of four sets of the above units.

[Problem to be solved by the invention]

As described above, according to the conventional method, each time the memory capacity is increased to a predetermined number of words, for example, 16 words, the number of memory elements or ICs (integrated circuits) increases by one, and the mounting space thereof increases. Nowadays, mechanical parts such as printed circuit boards and connectors now account for a large proportion of device prices due to advances in semiconductor technology that have led to lower prices for ICs.However, parity memory has the problem of increasing cost as devices become larger. Ta.

SUMMARY OF THE INVENTION An object of the present invention is to provide an odd-even check method that can reduce the number of memory elements for parity bits.

[Means to solve the problem]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, 2 is a parity memory in which one word has multiple bits, and each bit stores a parity bit of one data word in data memory 1; Means for reading one word of the parity memory 2 based on address information; 4 means for specifying the parity bit position for the data word based on the address information; 5 reading by the reading means 3 based on the designation of the specifying means 4; means for extracting a parity bit from one word written into the data memory 1; 6 means for performing an odd-even check on the read data word and the parity bit extracted by the extraction means 5 during read access; Means 8 for creating bits, during write access, places a parity bit created by the creation means 7 in a bit position designated by the designation means 4, and a parity bit read out by the reading means 3 in other bit positions. This is a means of writing in Memo+J2.

[Effect]

According to the invention, the reading means 3 reads one word storing the parity bits of the data word from the parity memory 2;
The specifying means 4 specifies the parity bit position for the data word, and the extracting means 5 specifies the parity bit position for the data word.
Based on the designation, the reading means 3 extracts a parity bit from one successive word, and the checking means 6 performs an odd-even check on the read data word and the parity bit extracted by the extracting means 5. Further, at the time of write access, the creation means 7 creates a parity bit from the write data to the data memory l, and the four-speed means 8 writes the parity bit from the creation means 7 to the bit position designated by the designation means 4, and the other Since the bits from the reading means 3 are written into the parity memory 2 at the bit positions, the memory for parity bits can be constructed from memory elements in which one word has a plurality of bits.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to FIG. The same reference numerals refer to the same objects throughout the design.

Components in FIG. 2 that correspond to those in FIG. 1 are surrounded by dashed lines.

In FIG. 2, data memory 1a has a storage capacity of 64 words (8 bits/word), and parity memory 2a has a storage capacity of 16 words (8 bits/word).
The 8 bits of each word are configured to store parity bits for the 8 words of the data memo 1/a.

[When reading data]

From the data memory 1a to the microprocessor (hereinafter referred to as MP)
Address signal AOO (LSD) ~A1 from U)
5 (MSD), one word of data specified as address I is read out, and address signal A0 is read out from parity memory 2a.
One word of parity data addressed by 3 to A15 is output one after another. The selector 5a selects AOO- from the parity data (including 8 parity bits) from the parity memory 2a.
One bit is selected by AO2 and the parity bit for the read data is extracted. The parity check/creator 6a performs a parity check on the read data and the parity bit extracted by the selector 5a to detect the presence or absence of data errors.

[When writing data]

Parity check/creator 6a receives write data to data memory la and creates parity bits. One word addressed by address signals A03 to A5 is read from the parity memory 2a. Decoder 4a is AOO~A
Decode O2 to specify the bit position in the parity data (8 bits) for the current write data. The writing unit 8a outputs the parity bit created by the parity checker/creator 6a to the bit position specified by the decoder 4a (AND circuit A2), and outputs the parity bit created by the parity checker/creator 6a to the bit position specified by the decoder 4a, and outputs the parity bit to the bit position designated by the decoder 4a (AND circuit A2).
The data read from the parity memory 2a is output as is (AND circuit A1) to the (NOT circuit 2) and written to the parity memory 'J2a (OR circuit OR).

Therefore, one word of the parity memory 2a corresponds to one word of the data memory 1a.
8 parity bits corresponding to 8 data words are stored, and the corresponding 8 parity bits are read from the parity memory 2a when the data memory 1a is read/written, and when data is read, the corresponding parity bits are extracted from the 8 parity bits. A parity check is performed together with the read data, and when data is written, a parity bit created from the 8 bits of write data is stored in a corresponding bit position of the 8 parity bits. Therefore, as explained in the conventional example, the parity memory that required four memory elements is now configured with one memory element.

This example is one embodiment of the present invention, and it goes without saying that there are many variations in the implementation method. Parity memory 2a
The required parity data is created from the ROM by addressing the 8 parity bits read from the ROM, the 1 + parity bit (address signals AOO to AO2 indicating recovery, and the value of the parity bit created by the parity check/creator 6a). Can be done.

〔Effect of the invention〕

As explained above, according to the present invention, the number of memory elements is reduced by using a memory element having multiple bits per word in the memory for parity bits, and the mounting space is reduced, thereby reducing the size of the device. This also has the effect of reducing costs.

4a is a decoder, 5 is an extraction means; 5a is a selector, 7 is the means of creation; 8 is a writing means; 8a is the writing section shows.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a memory configuration diagram showing a conventional example. In the figure, 1.1a is data memory, 2.2a is parity memory, 3 is reading means, 4 is specifying means, Σ

Claims (1)

[Scope of Claims] A parity memory (2) consisting of a memory element in which one word has a plurality of bits, each bit storing a parity bit of one data word of the data memory (1); and the data memory (1). means (3) for reading one word of the parity memory (2) based on the address information of the data word during read/write access of the data word; and means (3) for specifying the parity bit position for the data word based on the address information. 4) and the reading means (3) based on the designation of the designation means (4).
means (5) for extracting a parity bit from one word read by the extraction means (5); means (6) for performing an odd-even check on the read data word and the parity bit extracted by the extraction means (5) during read access; means (7) for creating a parity bit from data written to the data memory (1); and a parity created by the creation means (7) at a bit position designated by the designation means (4) during write access. bit, and the reading means (3) in other bit positions.
) for writing the bit read out into the parity memory 1 (2).