JPH04177697A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent increase in access time by separating a memory cell array, selecting a divided array block with a built-in decoder, and controlling the decoder output arbitrarily. CONSTITUTION:A memory cell array 1 such as 64 words is divided into four 16K-word memory cell array blocks 11-14 and the blocks 11-14 are selected through a built-in decoder 2. Then, the array 1 is controlled by an address A1 and addresses A2 and A3 are decoded by the decoder 2. An address signal through decoded address output lines 201-204 is controlled arbitrarily by a decoder output control circuit 3 according to a mode selection signal. The internal decoder in a configuration which does not use an external decoder and allows output to be controlled arbitrarily prevents a decoder output delay time from being superposed on a delay time such as a chip select signal, prevents increase in access time, and enables operation to be speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory in which the number of words and the number of input/output bits are variable.

[Conventional technology]

Conventionally, general-purpose semiconductor memories have a fixed number of words and a fixed number of input/output hits. Therefore, when dealing with an address space whose number of words is larger than that of a semiconductor memory chip,
This is achieved by using a semiconductor memory chip with a larger word count than the semiconductor memory chip, or by providing an external decoder and connecting the output of the external decoder to the chip select terminal of each memory chip.

FIG. 6 is a block diagram of a memory system using a semiconductor memory for explaining an example of such a conventional system.

As shown in FIG. 6, the conventional semiconductor memory system is
This is an example in which a 64-word memory system is constructed using four 16-word memory chips 71 to 74, a decoder 22, and a data line 501. In this example, of the 16 bits of the address pointing to word 64, 14 bits are input to address 104 of memory chips 71-74, and the remaining 2 bits are input to address 105 of decoder 22. The output lines 221 to 224 of this decoder 22 are connected to the chip select terminals of the memory chips 71 to 74, respectively.
- Connect to.

FIG. 7 is a timing diagram of access time when the semiconductor memory shown in FIG. 6 is used.

As shown in FIG. 7, the chip select access time in a semiconductor memory such as an SRAM has the same delay time as the address access time, and the delay time of the external decoder is directly increased to the access time delay time of the memory system.

[Problem to be solved by the invention]

The conventional semiconductor memory described above requires an external decoder when configuring a memory system with a larger number of words than the number of words of the memory chip.

Therefore, since the chip select access time of an SRAM or the like usually has the same delay time as the address access time, there is a drawback that the delay time of the external decoder is directly added to the delay time of the access time of the memory system.

An object of the present invention is to provide a semiconductor memory that prevents an increase in access time in such a memory system.

[Means to solve the problem]

The semiconductor memory of the present invention is a semiconductor memory having a word count of 2m, and includes a memory cell array divided into 2'' blocks (m>n), and a decoder for decoding n hints out of m input addresses. and a decoder output control circuit that arbitrarily controls the output of the decoder.
The input/output control circuit includes a data amplifier and a write amplifier that operate based on the output of the decoder output control circuit, corresponding to each block of the memory cell array.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a semiconductor memory showing a first embodiment of the present invention.

As shown in Figure 1, this embodiment uses address input (AI)
A memory cell array 1 including memory cell array blocks 11 to 14 connected to each other via an address input line 101, and a decoder 2 connected to address inputs (A2 and A3) via address input lines 102 and 103. ,
Connected to decoder 2 via decoder output lines 201 to 204 and mode selection signal input (A, E3) 801, 8
02, the outputs 301 to 304 of the decoder output control circuit 3, and the output enable signal (OE) 601. Based on the write enable signal (WE) 602, the outputs 111, 121, 131° 141 from the memory cell array 1 are transferred to the data input/output 51.
1,531,551.degree. 571 or write data from the data input/output terminals 511.degree. 531.551.571 into the memory cell array 1. In this semiconductor memory, a memory cell array 1 has 64 words, and in this example, memory blocks 11 and 12 each have 16 words.
, 13.14. Each of the memory blocks 11 to 14 inputs an address signal through a 14-bit address input line 101, and each outputs a 4-bit output 1.
Outputs 11,121°131.141. Also, the decoder 2 inputs 2-pit addresses 102 and 103,
One of the decoder outputs 201, 202, 203, and 204 is output as "H". The input/output relationship of the decoder 2 is as shown in the truth table in Table 1, and the decoder output control circuit 3 includes OR gates 31.32, AND gates 33.34, and 3-input OR gates 35 to 38. The mode selection signals 801, 802 control the outputs 201, 202, 203, 204 of the decoder 2, and the output lines 30
Control outputs are sent to 1° 302, 303, and 304.

Furthermore, the input/output control circuit 4 operates a logic game h41 that calculates the AND of the output lines 301, 302, 303, 304 of the decoder output control circuit 3 and the output enable signal 601.
, 43, 45, 47, the output lines 301, 302, 303, 304 of the decoder output control circuit 3, and the write enable signal 602.
6.48 and logic gate specific force lines 411, 431, 451
When ゜471 is at 'H'' level, the input/output lines 111, 121゜131.
141 to data input/output line 511, 531゜551.57
Data amplifier 51゜53.55.57 connected to 1,
Logic gate output line 421゜441.461,481 is “
When the data input/output lines 511, 531, 5 are at H” level,
51,571 data to the memory block input/output line 111
, 121° 131.141.
゜54.56.58.

Figure 2 shows a 16-bit memory chip using the semiconductor memory chip shown in Figure 1.
FIG. 2 is a block diagram of a word memory system.

As shown in FIG. 2, a 14-bit address signal indicating a word is input to address line 101, and address lines 102 and 103 are grounded. In this example, by fixing the mode selection signal 801 to "H" and fixing the mode selection signal 802 to "L", the outputs 301, 302, 30 of the Hiroshi Tecoder output control circuit 3 are
3゜304 are all “H”, address line 102゜10
3, the data input/output line 51 is activated based on the output enable signal 601 and the write enable signal 602.
It is possible to read or write to 1,531,551,571. Therefore, the semiconductor memory chip in this example functions as a 16K×16 memory chip.

FIG. 3 shows a 32-bit device using the semiconductor memory chip shown in FIG.
FIG. 2 is a block diagram of a word memory system.

As shown in FIG. 3, 14 bits of a 15-bit address signal indicating word 32 are supplied to address line 101, the remaining 1 bit is supplied to address line 102, and address line 103 is grounded. Further, by fixing the mode selection signal 801 to "L" and fixing the mode selection signal 802 to "H", the output line 201 of the decoder 2 is set to "Hn" when the address line 102 is "L".As a result, the first The output line 311 of the logic gate 31 shown in the figure becomes "H", the output line 331 of the logic gate 33 becomes "H", and the output lines 301 and 302 of the decoder output control circuit 3 become "H". Therefore, when address line 102 is at "L", 8 bits of data input/output lines 511 and 531 are used to read and write data. Similarly, address line 102 is
”, the output line 303°3 of the decoder output control circuit 3
04 becomes H'', data input/output line 551゜571 no 8
Data is read and written using bits.

That is, in this example, the semiconductor memory chip is 32KX8
functions as a memory chip.

FIG. 4 is an operation timing diagram of signals of each part of the semiconductor memory shown in FIG. 1.

As shown in FIG. 4, an example is shown in which the circuit operation of each part of FIG. 1 is applied to FIG. 3.

Furthermore, similarly, eight semiconductor memory chips of this embodiment are used, and mode selection signals 801 and 802 are both set to L.
By fixing the semiconductor memory chip to 64KX4
can function as a memory chip. The relationship between the mode selection signals 801 and 802 and the modes is shown in Table 2. FIG. 5 is a block diagram of a semiconductor memory showing a second embodiment of the present invention.

As shown in FIG. 5, this embodiment is different from the first embodiment shown in FIG. Similarly, the decoder output control circuit 3 and the input/output control circuit 4 are provided, and in addition to these, mote selection signals 801 and 8 are provided.
02 is provided with a register 7 controlled by a latch clock 701. This register 7 allows a mode selection hit pattern to be input from the data output line 571 and stored, so that a mote can be selected.

〔Effect of the invention〕

As explained above, the semiconductor memory of the present invention divides a memory cell array, allows a block of the divided memory cell array to be selected by a built-in decoder, and arbitrarily controls the output of the decoder. In addition to making the apparent configuration of the memory chip variable, it is also possible to eliminate the need for an external decoder by configuring a memory system with a number of words between a certain range in one memory chip, and the memory system due to the increased delay of the external decoder. This has the effect of preventing an increase in the overall access time.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor memory showing a first embodiment of the present invention, FIG. 2 is a block diagram of a 16-word memory system using the semiconductor memory chip shown in FIG.
FIG. 4 is a diagram showing the configuration of a 32-word memory system using the semiconductor memory chip shown in FIG. FIG. 6 is a block diagram of a semiconductor memory. FIG. 6 is a memory system configuration diagram using a semiconductor memory to explain a conventional example. FIG. 7 is a timing diagram of access time when using the semiconductor memory shown in FIG. 6. be. 1...Memory cell array, 2...Decoder, 3...Decoder output control circuit, 4...
...Input/output control circuit, 7...Register, 11
, 12, 13. 14... Memory cell array block, 31, 32, 35° 36. 37, 38...
・OR gate, 33.34...AND gate, 4
1~48...AND gate, 51.53,55
, 57...Data amplifier, 52°54.56.
58-=light 77b, 101°102.103...
...Address entry line, 111°121.131,14
1...Memory cell 7 rave o ivy output line, 2
01,202,203,204-=-data amplifier, 3
01,302,303,304...Decoder output control circuit output line, 311,321...OR gate output line, 331,341...ANDN-gate line, 411 ,421,431,441゜451.4
61,471,481...AND game IJ line of force, 501...Data line, 511°531.55
1,571... Data person output line, 601...
...Output enable full signal, 602...
-Write enable signal, 701... Latch clock signal line, 801, 802... Mode selection signal. Agent Patent Attorney Uchihara Onsho Figure 1 Figure 3 Attos input site Iρ / 4th field Z evening map

Claims (1)

[Claims] In a semiconductor memory with a word count of 2^m, 2^n
a memory cell array divided into blocks (m>n); a decoder for decoding n bits of an input m-bit address; a decoder output control circuit for arbitrarily controlling the output of the decoder; 1. A semiconductor memory comprising an input/output control circuit in which a data amplifier and a write amplifier that operate based on the output of the output control circuit are provided corresponding to each block of the memory cell array.