JPS6045505B2 - associative memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an associative memory device, and more particularly to an associative memory device whose word configuration (number of words×number of bits) can be changed.

Generally, associative memories are suitable for implementation with semiconductor integrated circuits.

Therefore, an associative memory having a fixed word structure has been realized by integrating a large number of memory cells on one chip. Furthermore, a plurality of such associative memory chips were used to realize an associative memory device with the necessary word structure. In this case, associative memory devices with different word configurations have been realized by changing the number of associative memory chips used. This was possible because the storage capacity of conventional associative memory chips was much smaller than that of the desired associative memory device. However, in recent years, the degree of integration of semiconductor circuits has improved dramatically, and it has become possible to integrate memory cells of considerable capacity on one chip, making it difficult to realize an associative memory device with the required word structure on a single chip. It has become possible.

In this case, if the word configuration of one chip is fixed as in the past, it is impossible to configure an associative memory device with a word configuration other than that implemented in this chip. For example, the chip cannot be used in devices that require fewer words and more bits per word than the number of words implemented on the chip. Therefore, if such an associative memory device with a fixed word structure is integrated, it will lack versatility and become expensive. The present invention has been made to eliminate the above-mentioned drawbacks, and is to realize an associative memory device whose word configuration can be arbitrarily changed by applying a control signal.

Furthermore, although it is possible to increase the memory capacity (both the number of words and the number of bits) by using a plurality of content addressable memory devices, this can be achieved with a smaller number of terminals than in the past. Therefore, if this is realized using a semiconductor integrated circuit, the chip will be highly versatile and the cost of the chip can be reduced. Hereinafter, the contents of the present invention will be explained in detail with reference to the drawings. FIG. 1 shows a first embodiment of the invention.

This example is an associative memory having a basic word structure of 4 words x n bits, and this example will be explained below, but the same applies to any number of words. In FIG. 1, 1 is a search data input line, 2 is a storage data input/output line,
3 to 6 each indicate an n-bit content addressable memory cell array.
7 to 10 are for reading and writing when reading and writing content addressable memory;
word lines, 11-1, specifying the word to be written to;
Reference numeral 4 denotes a match detection signal line on which associative processing is performed between search data and stored data, detects a certain kind of matching relationship, and outputs the result.

A control circuit 15 has a function of activating control output signal lines 17 to 20 according to the contents of the control input signal line 16.

21 to 24 are the corresponding word match detection signal lines 11
14 and the control output signal lines 17 to 20, and 25 to 28 are output lines thereof, and are associative result output lines indicating the associative results.

1 to 14 are similar to the configuration of a conventional associative memory device. There are other parts newly added according to the present invention. The operations in FIG. 1 are as follows.

First, a case will be described in which this associative memory is operated with a basic word configuration of 4 words x n bits. Associative: There are three memory operating modes: read, write, and search. Of these, for reading and writing,
By specifying any of the word lines 7 to 10, the storage information of the corresponding word is read to the storage data input/output line 2, or the information of the storage data input/output line 2 is written to the corresponding ζ word. It will be done. In the search mode, the control circuit 15
By setting all the output signals 17 to 20 to ゜゜1゛ (activation), the states of the coincidence detection signal lines 11 to 14 of each word appear as they are on the association result output lines 25 to 28. Therefore, it can be seen that in this case, the operation is exactly the same as that of the conventional associative memory device. Next, a case will be described in which FIG. 1 is used as an associative memory device having a word structure of 2 words×additional bits. At this time, it is assumed that the content addressable memory cell arrays 3 to 6 are allocated as follows. That is, the top n of the first word
Memory cell array 3 for the bit, memory cell array 4 for the lower n bits, memory cell array 5 for the upper n bits of the second word, memory cell array 6 for the lower n bits.
Suppose we assign . In this case, since the upper n bits and the lower n bits are operated separately, twice the number of clocks required to operate with the basic word configuration is required. First, to explain the read mode, when reading the first word, only the word line 7 is set to ゜゜1゛ in the first cycle, the upper n bits stored in the content addressable memory cell array 3 are read, and the word line 7 is read out in the second cycle. Only the line 8 is set to ``1'', and the lower n bits stored in the content addressable memory cell array 4 are read out. Similarly, the second word can be read by sequentially setting the word lines 9 and 10 to ``1''. The write mode is similar, and word lines 7 to 10 may be designated to write the upper n bits in the first cycle and the lower bits in the second cycle. Next is the search mode. In this case, the search data given to the search data input line 1 is n bits, so it is necessary to determine whether this search data is for the upper n bits or the lower n bits of each word. It is necessary to distinguish and output associative results.

Therefore, for example, in the first cycle, search the upper n bits,
If the lower n bits are searched in the second cycle, then the control circuit 15 outputs the output signals 17, 1 in the first cycle.
9 as ゜゜1゛, output signals 18, 20 in the second cycle
The control input signal line 16 is set so that "1" is set. Then, the associative result appears on the coincidence detection signal lines 11 to 14 every cycle, but the associative result output lines 25 to 28
In the first cycle, 25 and 27 are the match detection signal lines 11 and 1 indicating the association result of the upper n bits of each word.
Similarly, in the second cycle, the information of 26 and 2 is output.
8 outputs information on match detection signal lines 12 and 14 indicating the association result of the lower n bits of each word. In this way, even when the content addressable memory cell arrays 3 to 6 are used in a word configuration of 2 words x additive bits, each word is correctly compared with the search data by the upper n bits and the lower n bits, and the search mode is executed. FIG. 2 shows a second embodiment of the invention.

In the figure, 1 to 14 are conventional associative memory devices;
It is the same as the figure. 29 is a maskable address decoder, 30 is an address input line, 31 is a mask information line, 3
2 to 35 are output lines of the address decoder 29.

Numerals 36 to 39 are AND gates which apply the decoded output from the address decoder 29 to the word lines 7 to 10 of the associative memory cell arrays 3 to 6 when the read/write mode designation signal line 40 is at .degree.1.

41 to 44 are data selectors, which output the AND of the output lines 32 to 35 of the address decoder 29 and the match detection signal lines 11 to 14 of the associative memory cell arrays 3 to 6 when the address associative designation signal line 45 is "1". However, when the address association designation signal line 45 is "0", it has a function of outputting the information on the coincidence detection signal lines 11 to 14 as is.

46 to 49 are associative result output lines.

The embodiment shown in FIG. 2 uses, as the control circuit 15 shown in FIG. 1, a circuit in which logic is added to the address decoder used for writing and reading to make it maskable.

Normally, an address decoder is required for reading and writing, and using it also as a control circuit requires far less hardware and is more convenient than adding a control circuit in addition to the address decoder. Good. The function of this maskable address decoder 29 is as follows.

The 2-bit mask information line 31 does not mask when it is ``00'', and in this case the decoder 29 outputs the address input line 30.
As a result of decoding the address information, any one of the output lines 32 to 35 is set to ゜゜1゛.

For example, when the address is (010), the output line 32, when it is (0, 1), the output line 33, when it is (1, 0), the output line 34, and when it is (1, 1), it is the output line. The line 35 becomes "°1". On the other hand, when an arbitrary bit of the 2-bit mask data is set to "°1", the bit of the same order as this bit of the address is masked and decoded regardless of the data of that bit. For example, if the mask data is (1, 0), when the address is (0, 0) or (1, 0), the output lines 32 and 34 are set to 66r2, and when the address is (0, 1) or (1, 1), the output lines 32 and 34 are set to 66r2. In this case, the output lines 33 and 35 become "1". Similarly, if the mask data is (0.1), when the address is (0, 0) or (0, 1), the output line 32,
33 is “゜1゛”, the address is (1, 0) or (1,
In the case of 1), the output lines 34 and 35 become "1".Next,
The operation of the associative memory device shown in FIG. 2 using the above decoder will be explained.

First, when used as a device with a basic word configuration, that is, 4 words x n bits, the mask data is set to "°00" and the decoder 29 is used without masking.
In the read and write modes, the address input line 30
, and set the read/write mode designation signal line 40 to “
1, and supplies the output of the decoder 29 to any one of the word lines 7 to 10 of the content addressable memory cell arrays 3 to 6;
The storage contents of the selected word are read out to the input/output data line 2, or the data on the input/output data line 2 is written into the corresponding cell array. In the search mode, by setting the read/write mode designating signal line 40 to 0.degree., the word lines 7 to 10 are all set to 0.degree., and the search data supplied to the search data line 1 is searched. At this time, the address association designation signal line 45
is set to "0", and the information on the match detection signal lines 11 to 14 corresponding to each word is sent as is) to the association result signal lines 46 to 4.
Output to 9. Next, a case will be described in which FIG. 2 is used in a 2 word x nod bit configuration. At this time, it is assumed that the content addressable memory cell arrays 3 to 6 are allocated as follows. j i.e.
Memory cell array 3 is allocated to the upper n bits of the first word, memory cell array 4 is allocated to the lower n bits, memory cell array 5 is allocated to the upper n bits of the second word, and memory cell array 6 is allocated to the lower n bits. As in Figure 1, in this case the upper n bits and the lower n hits are operated separately, so
2 of the number of clocks required to operate with the basic word configuration
Requires twice the number of clocks. In the read mode, when reading the first word, the word line 7 is set to "1" in the first cycle, the upper n bits stored in the associative memory cell Afray 3 are read, and in the second cycle, only the word line 8 is set to "1". is set to ゜゜1゛, and the lower n bits stored in the content addressable memory cell array 4 are read out.For this purpose,
Connect read/write mode signal line 40 to ゜“1゛, mask information line 3
1 is (0, O), and the address input line 30 supplies (a), 0) in the first cycle and (i), 1) in the second cycle. Similarly, the second word is (1, 0) in the first cycle.
, (1, 1) may be supplied to the address input line 30 in the second cycle. Even in search mode, the search data supplied from search data line 1 is n bits, so whether the search data is given to the upper n bits of each word or to the lower n bits. It is necessary to output the association results by distinguishing between the two. Therefore, for example, when search data is given to the upper n bits, the address input line 30 is set to (0, 0) or (1, 0).
), and the mask data of the mask information line 31 is (1, 0).
As a result, the decoder output lines 32 and 34 are set to "1", the address associative designation signal line 45 is set to "1", and among the coincidence detection signals output from each associative memory cell array 3 to 6, signal lines 11 and 13 are set to "1". Only the information on the associative result signal line 4
6, 48, and the remaining associative result signal lines 47, 49
is set to "0" regardless of the information on the signal lines 12 and 14. At this time, the read/write mode signal line 40 is set to "'0". When search data for the lower n bits is given, the address is (a), 1) or (1, 1).
), and by setting the mask data to (1, 0), decoder output lines 33 and 35 can be set to ``1''.
In addition, when giving search data over an additional bit, 2
Search by cycle. For example, if you want to search the upper n bits in the first cycle and the lower n bits in the second cycle, set the mask data to (1, 0) and set the address (a), 0) or ( 1, 0), and in the second cycle set the address to (a), 1) or (1, 1)
And it is sufficient. FIG. 3 shows a third embodiment of the invention.
This corresponds to the maskable address data in the embodiment of FIG. A maskable second associative memory is used instead of a coater. 50 to 53 constitute each word of the second content addressable memory.

The coincidence detection signals of the second content addressable memories 50 to 53 are
are supplied to the words corresponding to the associative memory devices of 41 to 41.
The decoder shown at 44 follows the same logic as the embodiment of FIG. The search data in the second associative memories 50 to 53 is processed using a mask circuit 57 based on address information 54 and mask data 55 so that associative processing is performed regardless of the bits designated by the mask data. It is something. Such a maskable associative memory has conventionally been easily created. Taking 2 bits as the address information 54 as an example, this second content addressable memory 50~
53 is 2 bits per word. The search data in the second content addressable memories 50 to 53 becomes the address information 54 itself when the 2-bit mask data 55 is (a), 0). Therefore, each of the second content addressable memories 50 to 53 (
0, 0), (0, 1), (1, 0), (1, 1) is stored as address information (a), 1)
, the coincidence detection signal line 33 of the cell array 51 that stores the same information becomes "1".At this time, if the mask data 55 is set to (1, 0), the specified bit is Since it is masked, address information (0, 1)
is (×, 1) as the search data in the second associative memory 5.
0 to 53. In this), × indicates that the associative processing is invalid. Therefore, in this case, (a), 1) and (
The coincidence detection signal lines 33 and 35 of the cell arrays 51 and 53 that store 1, 1) become "1". In other words, the function of the maskable address decoder 29 shown in FIG. 2 can be easily realized. Since the method checks whether part or all of the search data matches the stored information, it is suitable for decoding masked data, and this function can be easily realized without using complicated logic gates.

Note that when writing stored data into the second content addressable memories 50 to 53, a data input line 56 and a word line 58 are used. Since this stored data is an address and is fixed, the second associative memory can also be realized by an associative ROM. As described above, according to the present invention, the word configuration of an associative memory device can be changed by a control signal, so when this device is configured with a semiconductor integrated circuit, the versatility of the chip increases.

When using a large number of chips to realize a word configuration larger than the number of words and bits configured within the chip, by increasing the number of bits per word within the chip and increasing the number of chips, It is also possible to increase the number of words. Therefore, the associative memory device according to the present invention not only allows a word configuration, but also has the expandability of expanding the storage capacity (number of words, number of bits) by using a plurality of them. Conventionally, in order to expand the number of bits per word, multiple content addressable memory chips were used and the coincidence detection signals of all chips corresponding to the same word were ANDed. However, since the present invention can be expanded within a chip, there is no need to provide a coincidence detection signal terminal for expandability. Therefore, a large-capacity content addressable memory can be realized at low cost with a small number of terminals.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a content addressable memory device according to a first embodiment of the present invention, which has a basic configuration of 4 words x n bits, and FIG.
FIG. 3 shows a third embodiment in which a maskable decoder is used as the control circuit in FIG. 1, and a maskable second associative memory is used as the control circuit in FIG. FIG. DESCRIPTION OF SYMBOLS 1... Search data input line, 2... Storage data input/output line, 3-6... Content addressable memory cell array, 15... Control circuit, 21-24... ...AND gate, 29...Address decoder, 30...
...Address input line, 31...Mask information line,
36-39...AND gate, 41-44...
...Data selector, 50-53...Second content addressable memory.

Claims (1)

[Scope of Claims] 1. An associative memory device that inputs search data, performs associative processing between the search data and stored information stored in a memory, and outputs the associative results corresponding to words in the memory,
A control circuit having an output line corresponding to each word is added, and the output line can selectively activate one or more than two at the same time, and the output line corresponds to the activated output line. An associative memory device characterized by validating associative results. 2. In the associative memory device according to claim 1, the control circuit masks arbitrary bits of input address information and decodes the address regardless of the information of the masked bits. An associative memory device characterized by using an address decoder having a function of activating one or two or more output lines at the same time. 3. In the associative memory device according to claim 1, the control circuit includes a second associative memory that performs associative processing between all or part of the search data and the stored information, and outputs the associative results in word correspondence. An associative memory device characterized in that it is used.