JPH01159729A - Symbol string collation memory and its cascade connection system - Google Patents

Abstract

PURPOSE:To enable cascade connection by controlling a cascade output terminal and a coincidence signal output terminal so as to be active/inactive according to which an input terminal for the cascade connection is active/inactive. CONSTITUTION:The system is constituted of the input terminal 19 and the output terminal 25 for the cascade connection and a controlling means 20. Data synchronizing with an external clock from the input terminal 12 is inputted from the input terminal 11, and is compared with a pattern string registered in a shift register 13 and an associative memory 14 in real time, and a comparison result signal 26 is outputted. As for an address in which coincidence occurs, the output from an encoder 15 enters the controlling means 20, and when the input terminal 19 is active, the output terminal 16 turns to be inactive independently of an all coincidence signal from the memory 14. A multiple coincidence signal output terminal 17 turns to be inactive only while the coincidence does not occur in the memory 14.

Description

[Detailed description of the invention] [Industrial application field] INDUSTRIAL APPLICABILITY The present invention is utilized in the field of digital information and communications.

The present invention relates to a symbol string matching memory used in digital information communication and its cascade connection system, and in particular to a CPU
The present invention relates to a symbol string matching memory and a cascade connection method thereof, in which the registered button symbol string capacity can be expanded without changing the interface with the symbol string.

〔overview〕

The present invention stores a predetermined symbol string in a storage means in advance, compares this stored symbol string with a matching symbol string inputted from the outside, and generates a match signal indicating that a match exists, and generates a match signal indicating that a match exists. A symbol string matching memory that outputs a multiple match signal indicating the existence of a match and an address code in which a match exists, is provided with an input terminal for cascade connection and an output terminal for cascade connection, and is configured to determine whether the input terminal for cascade connection is active or inactive. Accordingly, the cascade connection is made possible by controlling the output terminal for cascade connection, the coincidence signal output terminal, and the multiple coincidence signal output terminal to be active or inactive.

[Conventional technology]

Conventionally, this type of symbol string matching memory has a shift register 13 operated by an external clock input from an external clock input terminal 12 and a plurality of addresses, as shown in FIG. 13, and compares the contents of the shift register 13 with the contents stored in the storage means at all addresses in parallel, and outputs a comparison result signal 26 indicating whether or not they match for each address. an associative memory 14 which inputs the comparison result signal 26 and generates a coincidence signal 27 when there is a coincidence, a multiple coincidence signal 28 when there is a plurality of coincidences, and the storage means that encodes the comparison result signal 26 and generates a coincidence. A priority encoder (P
ECD) 15, a coincidence signal output terminal 16, a multiple coincidence signal output terminal 17, and an address code output terminal 18, which output a coincidence signal 27, a multiple coincidence signal 28, and an address code 29, respectively.

The priority encoder 15 then develops the inputs and outputs shown in FIG. 4, and performs operations according to the truth table shown in Table 1. In other words, among 2'' inputs (n is a natural number) - at any time r) (if J exists, the single match (SM) output is r
I (J), and if there are multiple H, multi-match (MM
) output becomes "H", Q+"'-Ql, and n predetermined encoded outputs are output from the output. In other words, the single match output becomes a match signal 27, and the multi-match output becomes a multiple match signal. The signal becomes 28, and the Q,
-Q, the output becomes address code 29.

[Problem that the invention seeks to solve]

The conventional symbol string matching memory mentioned above did not have a terminal for cascade connection, so when using multiple conventional symbol string matching memories, it is necessary to check whether there is a match or not, and check the matching address code results for each symbol string matching. It is necessary to read each memory individually, and as the number of symbol string matching memories increases,
This method has the disadvantage that the processing time required to obtain the matching results increases. Furthermore, when a certain symbol string is input and a match occurs in a plurality of symbol string collation memories, there is a drawback that an external circuit or software needs to be added in order to determine multiple matches.

An object of the present invention is to provide a cascade-connectable symbol string matching memory and its cascade connection method by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The symbol string matching memory of the present invention includes a shift register operated by an external clock, a plurality of addresses, each address has a storage means of the same size as the shift register, and the contents of the shift register and the information at all addresses are stored. A storage comparison means that compares the contents stored in the storage means in parallel and outputs a comparison result signal indicating whether or not there is a match for each address; and a storage comparison means that inputs the comparison result signal and outputs a match signal when a match exists. and a priority encoder that encodes the comparison result signal and outputs a multiple match signal and an address code of the storage means that match when there is a plurality of matches; The symbol string matching memory includes a match signal output terminal to output, a multiple match signal output terminal, and an address code output terminal. In the case of input, the coincidence signal output terminal is inactive regardless of the output of the coincidence signal, the cascade connection output terminal is active, and the multiple coincidence signal output terminal is active when the coincidence signal is output. , inactive when the match signal is not being output, when the input terminal for cascade connection is an inactive input, the output terminal for cascade connection is active when the match signal is output, and when it is not output. is characterized in that it is equipped with control means for controlling each inactively.

The cascade connection system of symbol string matching memories of the present invention includes a plurality of symbol string matching memories of the present invention, and the input terminal for cascade connection and the output terminal for cascade connection of the first symbol string matching memory are each grounded. potential and the cascade connection input terminal of the second symbol string matching memory, and the matching signal output terminals of the first and second symbol string matching memories are respectively connected to the input of a second priority encoder. , the multiple signal output terminals are each connected to the input of a logic circuit that performs a predetermined logical operation, the address code output terminal is commonly connected to one bus together with the output of the priority encoder, and the output of the logic circuit is connected to the input of a logic circuit that performs a predetermined logical operation. It is characterized in that it is connected to the coincidence output signal line, and similarly connected to third, fourth, , etc. symbol string matching memories.

[Effect]

The control means defines whether the cascade connection output terminal, the coincidence signal output terminal, and the multiple coincidence signal output terminal are active or inactive, depending on whether the cascade connection input terminal is active or inactive. Therefore, when performing cascade connection, the input terminal for cascade connection of the first symbol string matching memory is grounded and made inactive, and the output terminal for cascade connection is connected to the input terminal for cascade connection of the second symbol string matching memory. do. In this case, when a match occurs in the first memory, the cascade connection input terminal of the second memory becomes active, and its match signal output terminal becomes inactive as a match signal is generated, and its multiplexed signal output The terminal becomes active.

As a result, if a match signal is generated in both the first and second memories, the match signal output terminal of the first memory is active, the multiple match signal output terminal is inactive, and the match signal output terminal of the second memory is inactive. The coincidence signal output terminal becomes inactive, and the multiple signal output terminal becomes active.

Therefore, by comprehensively determining the logical state of each match signal output terminal and each multiple match signal terminal, for example, the match signal is determined by a priority encoder, and the multiple match signal is determined by an OR gate, the match signal output in the case of cascade connection, the multiple match signal You can get the output and its address code.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the symbol string matching memory of the present invention. The symbol string matching memory of this embodiment includes a finite-length shift register 13 that shifts a plurality of n data input from a data input terminal 11 in response to an external clock input from a clock input terminal 12, and a finite-length shift register 13 that shifts a plurality of n data input from a data input terminal 11, and a plurality of addresses. Each address has a storage means of the same size as the shift register 13, and the contents of the shift register 13 and the contents stored in the storage means at all addresses are compared in parallel to determine whether or not they match for each address. an associative memory 14 as a storage comparison means that outputs a comparison result signal 26 shown in FIG. a priority encoder 15 which encodes the comparison result signal 26 and outputs the matched address code 29 of the storage means; a match signal output terminal 16 which outputs a match signal 27, a multiple match signal 28 and an address code 29, respectively; Signal output terminal 17, address code output terminal 18, and cascade connection input terminal 19
When the output terminal 25 for cascade connection and the input terminal 19 for cascade connection are active inputs, the match signal output terminal 16 is inactive regardless of the output of the match signal 27, and the output terminal 25 for cascade connection is active. When the input terminal 19 for cascade connection is an inactive input, the output terminal 25 for cascade connection receives the match signal 2.
The control means 20 is active when 7 is output, and inactive when it is not output.
It is equipped with

The control means 20 has a two-input OR gate 21 whose one input is connected to the cascade connection input terminal 19 and whose output is connected to the cascade connection output terminal 25, and one inverting input of which is connected to one input of the OR gate 21. The other input is connected to the match signal 27 and the output is the OR gate 2.
AND gate 22 with two inputs connected to the other input of AND gate 1 and the match signal output terminal 16; It includes an input AND gate 23 and a two-input OR gate 24 whose one input is connected to the output of the AND gate 23, the other input is connected to the multiple coincidence signal 28, and the output is connected to the multiple signal output terminal 17. There is. Note that this embodiment shows the case of active r)(j.

A feature of the present invention is that, in FIG. 1, a cascade connection input terminal 19, a cascade connection output terminal 25, and a control means 20 are provided and connected as shown.

Next, the operation of this embodiment will be explained. First, the logical operation of the control means 20 will be explained. Table 2 shows the truth table of logical operations. That is, the control means 20 performs the control operation as follows.

■ When the input terminal 19 for cascade connection is active, - Match signal output terminal 16 is inactive, - Multiple signal output terminal 17 is active when a match signal is output, and inactive when a match signal is not output, - Cascade connection The output terminal 25 is active.

■ When the cascade connection input terminal 19 is inactive, - The match signal output terminal 16 is active when a match signal is output, and inactive when a match signal is not output. - The multiple match signal output terminal 17 is used to output multiple match signals.・The cascade connection output terminal 25 is active when a match signal is output, and inactive otherwise.

Input the external clock from the external clock input terminal 12,
When data synchronized with this is input from the data input terminal 11, the shift register 13 and all pattern symbol strings registered in advance in the associative memory 14 are compared in parallel in real time, and a comparison result signal 26 is output. Then, corresponding to the address where the match occurred, the priority encoder 1 is
The I signal line, which is the input of 5, becomes active. The output from the priority encoder 15 is controlled by the control means 20, so that when the cascade connection input terminal 19 is active, the coincidence signal output terminal 16 becomes inactive regardless of the all coincidence signal from the associative memory 14, and multiple coincidence signals are output. The terminal 17 is inactive only when no match occurs in the associative memory 14, and active otherwise. Furthermore, when the cascade connection input terminal 19 is inactive, the match signal output terminal 16 becomes active when a match occurs in the associative memory 14, and the multiple match signal output terminal 17 becomes active only when a plurality of matches occur. Becomes active. The cascade connection output terminal 25 becomes active when the cascade connection input terminal 19 is active or when the coincidence signal output terminal 16 is active.

FIG. 2 is a block diagram showing an embodiment of the cascade connection method of symbol string matching memories of the present invention, in which two cascade-connectable symbol string matching memories of the present invention shown in FIG. 1 are cascaded. It is. In this embodiment, the first symbol string collation memory 31 including the associative memory 32, the second symbol string collation memory 33 including the associative memory 34, and the inputs of the first and second symbol string collation memories 31 and 33, respectively. A connected data bus 35 and a clock signal line 36,
a grounding wire 37 for fixing the cascade connection input terminal 19 of the first symbol string matching memory 31 inactive;
A signal line 38 connecting the cascade connection output terminal 25 of the first symbol string verification memory 31 and the cascade connection input terminal 19 of the second symbol string verification memory 33 and the A bus 39 in which multiple matching address code outputs are connected, and a matching signal output terminal 16 whose input is the first and second symbol string matching memories 31 and 33
and a priority encoder 40 connected by signal lines 41 and 42, and one input of which is connected to the first symbol string matching memory 3.
an OR gate 43 connected to the multiple coincidence signal output terminal 17 of the second symbol string collation memory 33 by a signal line 44 and whose other input is connected to the multiple coincidence signal output terminal 17 of the second symbol string collation memory 33 by a signal line 45;
, an output signal line 46 connected to the output of the OR gate 43 and indicating that there is a multiple match in at least one of the cascade-connected first and second symbol string collation memories 31 and 33, and a match address code output bus 39. Together with the output of the priority encoder 40, the associative memory 3
2 and 34.

The feature of the present invention is that the first symbol string matching memory 31 and the second symbol string matching memory 32 are connected as shown in FIG. 2 using a priority encoder 40 and an OR gate 43. be.

Next, the operation of this embodiment will be explained. Associative memory 32
The associative memory 3 stores the symbol strings rABcDEF and rXYZJ at addresses "00" and "01" in the content addressable memory 3.
4, register the bang symbol string ``○PQR3TUJrXYZJ'' in addresses ``00'' and ``01'' in advance.
When the matching symbol string rABCDEF is input from the data bus 35 in synchronization with the clock, a match occurs in the associative memory 32, and the matching address code "rABCDEF" is input to the bus 39.
00'', the signal lines 38 and 41 are active outputs, and the output bus 47 outputs the matching address code r000J.

At this time, the signal lines 44, 42 and 45 are inactive outputs, and the address code output terminal 18 of the symbol string collation memory 33 is high impedance. Similarly, when the matching symbol string rOPQR3TU is input from the data bus 35, a match occurs in the associative memory 34, a matching address code "00" is output to the bus 39, the signal line 42 becomes an active output, and the output bus 47 becomes "100".

At this time, the signal lines 38, 41, 44 and 45 are inactive outputs, and the address code output terminal 18 of the first symbol string collation memory 31 becomes high impedance.

Next, in the same way, from the data bus 35, the verification symbol string rXY
When ZJ is input in synchronization with an external clock from clock signal line 36, a match occurs in both content addressable memories 32 and 34. At this time, the bus 39 becomes the match address code "01" and the signal lines 41 and 38 become active outputs. Since the signal line 38 for cascade connection is active, the signal line 42 is inactive and the address code output terminal 18 of the symbol string matching memory 33 becomes high impedance even though a match has occurred in the associative memory 34. .

Further, although the signal line 44 is inactive, the signal line 45 becomes an active output, and the output signal line 46 also becomes active, indicating that multiple matches have occurred in the cascade-connected first and second symbol string matching memories 31 and 33. I understand.

In addition, in the embodiment of the connection method described above, the case where two symbol string matching memories are connected in cascade is shown, but even if three or more symbol string matching memories are connected, they can be sequentially connected in cascade in the same way as the second symbol string matching memory. can.

In addition, although the above description has been made using active r) (J, the same applies to the case of active r L J by reversing the logic.

〔Effect of the invention〕

As explained above, by having the above-mentioned means, the present invention makes it possible to cascade-connect several symbol string collation memos 'Jffl, and in that case, from the CPU, one It looks like a large-capacity symbol string matching memory, and has the effect of easily expanding the registration button capacity. Further, there is an effect that the occurrence of multiple coincidences across a plurality of LSI chips can be easily detected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of a symbol string matching memory of the present invention. FIG. 2 is a block diagram showing a second embodiment of the cascade connection system of symbol string matching memories of the present invention. FIG. 3 is a block diagram showing a conventional symbol string matching memory. FIG. 4 is an explanatory diagram of the priority encoder. 11...Data input terminal, 12...External clock input terminal, 13...Shift register, 14.32.34
... Content addressable memory, 15.40 ... Priority encoder (PECD), 16 ... Match signal output terminal,
17... Multiple coincidence signal output terminal, 18... Address code output terminal, 19... Cascade connection input terminal, 20... Control means, 21.24.43... OR gate, 22.23. ...AND gate, 25...Output terminal for cascade connection, 31.33...Symbol string matching memory, 35...Data bus, 36...Clock signal line, 37...Grounding line, 38. 41.42.44.45
...Signal line, 39...Bus, 46...Output signal line, 47...Output bus.

Claims (2)

[Claims] (1) Shift register operated by external clock (
13), each address has a plurality of addresses, each address has a storage means of the same size as the shift register, and the contents of the shift register are compared in parallel with the contents stored in the storage means at all addresses. storage comparison means (14) for outputting a comparison result signal indicating whether or not there is a match for each address; a priority encoder (1) that encodes the comparison result signal and outputs a matching signal and an address code of the storage means that matches;
5), a match signal output terminal (16), a multiple match signal output terminal (17), and an address code output terminal (1) that output the match signal, multiple match signal, and address code, respectively.
8), comprising a cascade connection input terminal (19) and a cascade connection output terminal (25), and when the cascade connection input terminal is an active input, the coincidence signal The output terminal is inactive regardless of whether the match signal is output, the cascade connection output terminal is active, the multiple match signal output terminal is active when the match signal is output, and inactive when it is not output. , control means for controlling the cascade connection output terminal to be active when the coincidence signal is being outputted and inactive when it is not being outputted when the cascade connection input terminal is an inactive input; (20) A symbol string matching memory characterized by comprising: (20). (2) A shift register operated by an external clock, having a plurality of addresses, each address having storage means of the same size as the shift register, and storing the contents of the shift register and the storage means at all addresses. storage comparison means for comparing the contents in parallel and outputting a comparison result signal indicating whether or not there is a match for each address; inputting the comparison result signal and outputting a match signal when there is a match; a priority encoder that outputs a multiple match signal and an address code of the storage means that encodes the comparison result signal and matches the match signal when present; and a match signal output terminal that outputs the match signal, the multiple match signal, and the address code, respectively. , a multiple match signal output terminal, an address code output terminal, a cascade connection input terminal, a cascade connection output terminal, and when the cascade connection input terminal is an active input, the match signal output terminal outputs the match signal. is inactive regardless of the output, the output terminal for cascade connection is active, and the input terminal for cascade connection is inactive,
The cascade connection output terminal is provided with a plurality of symbol string collation memories each having a control means that controls the output terminal to be active when the coincidence signal is being outputted and to be inactive when it is not being outputted. The input terminal for cascade connection and the output terminal for cascade connection of the column matching memory (31) are respectively connected to ground potential and the input terminal for cascade connection of the second symbol string matching memory (33), and the first and The coincidence signal output terminals of the second symbol string matching memory are respectively connected to the inputs of the second priority encoder (40), and the multiplex signal output terminals are respectively connected to the inputs of a logic circuit (48) that performs a predetermined logical operation. The address code output terminal and the output of the priority encoder are commonly connected to one bus (47), and the output of the logic circuit is connected to a multiple coincidence output signal line (46).
A cascade connection system for symbol string matching memories, characterized in that a third, fourth, .