JPH0748309B2 - Symbol string matching memory and its cascade connection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is used in the field of digital information communication.

The present invention relates to a symbol string collation memory used for digital information communication and a cascade connection system thereof, and more particularly, to a symbol string collation memory and a cascade connection system thereof in which a registered pattern symbol string capacity can be expanded without changing an interface with a CPU. Regarding

〔Overview〕

The present invention stores a predetermined symbol string in the storage means in advance, compares the stored symbol string with a collation symbol string input from the outside, and a match signal indicating that a match exists,
In a symbol string collation memory that outputs a multiple match signal indicating that there are a plurality of matches and an address code where there is a match, an input terminal for cascade connection and an output terminal for cascade connection are provided, and the input terminal for cascade connection is The cascade connection is made possible by making it possible to control the output terminal for cascade connection, the coincidence signal output terminal, and the multiple coincidence signal output terminal to be active or inactive according to active or inactive.

[Conventional technology]

Conventionally, as shown in FIG. 3, a symbol string collation memory of this type has a shift register 13 which operates by an external clock input from an external clock input terminal 12 and a shift register having a plurality of addresses. A comparison result signal 26 having a storage means of the same scale as 13 and comparing the contents of the shift register 13 with the contents stored in the storage means at all addresses in parallel and showing whether or not each address matches.
An associative memory 14 that outputs a match result signal 27 when there is a match by inputting the comparison result signal 26, a multiple match signal 28 when there is a plurality of matches, and a match result obtained by encoding the comparison result signal 26. A priority encoder (PECD) 15 for outputting the address code 29 of the storage means, a coincidence signal 27,
A match signal output terminal 16 for outputting a multiple match signal 28 and an address code 29, a multiple match signal output terminal 17, and an address code output terminal 18 are provided.

The priority encoder 15 has the inputs and outputs shown in FIG. 4, and operates according to the truth table shown in Table 1. That is, if even one of 2 ⁿ (n is a natural number) input has "H", the single match (SM) output is "H", and if there are multiple H, the multi-match (MM) output is "H".
Therefore, the predetermined number _{n of} outputs are output from the Q _{1 to} Q _n outputs. That is, the single match output becomes the coincidence signal 27, the multi-match output becomes the multiple coincidence signal 28, and the Q _{1 to} Q _n outputs become the address code 29.

[Problems to be solved by the invention]

Since the conventional symbol string collation memory described above does not have terminals for cascade connection, when multiple conventional symbol string collation memories are used, it is determined whether or not they match, and the matching address code result is compared with each symbol string collation. It is necessary to read each memory individually, and as the number of symbol string matching memories used increases,
Get the matching result However, there is a drawback that the processing time until it increases. Further, when a certain symbol string is input, if a plurality of symbol string matching memories are matched, there is a drawback that an external circuit or software needs to be added in order to judge a multiple match.

SUMMARY OF THE INVENTION An object of the present invention is to provide a symbol string collation memory capable of cascade connection and a cascade connection method thereof by eliminating the above drawbacks.

[Means for solving problems]

The symbol string collation memory of the present invention has a shift register operated by an external clock, and a storage means having a plurality of addresses and each address having the same scale as that of the shift register. Storage comparison means for comparing the contents stored in the storage means in parallel and outputting a comparison result signal indicating whether or not there is a match for each address, and a match signal when the comparison result signal is input and there is a match A priority encoder that outputs a multiple coincidence signal when a plurality of coincidences exist, and encodes the comparison result signal and outputs the coincident address code of the storage means, and the coincidence signal, the multiple coincidence signal and the address code, respectively. A symbol string collation device having a match signal output terminal for outputting, a multiple match signal output terminal, and an address code output terminal. In the above, the input terminal for cascade connection and the output terminal for cascade connection are provided, and when the input terminal for cascade connection is an active input, the match signal output terminal is inactive regardless of the output of the match signal, The cascade connection output terminal is active, the multiplex coincidence signal output terminal is active when the coincidence signal is output, inactive when the coincidence signal is not output, and when the cascade connection input terminal is inactive input Is provided with control means for controlling the cascade connection output terminal to be active when the coincidence signal is being output and inactive when the coincidence signal is not being output.

The cascade connection system of the symbol string collation memory of the present invention comprises a plurality of the symbol string collation memories of the present invention, and the cascade connection input terminal and the cascade connection output terminal of the first symbol string collation memory are respectively grounded. The potential and the second symbol string matching memory is connected to the cascade connection input terminal, the first and second symbol string matching memory the match signal output terminals are respectively connected to the input of the second priority encoder, The multiple signal output terminals are respectively connected to inputs of a logic circuit for performing a predetermined logical operation, the address code output terminals are commonly connected to one bus together with the output of the second priority encoder, and the output of the logic circuit is provided. Is connected to the multiple coincidence output signal line, and similarly, the third, fourth, ... Symbol string matching memories are also connected. And wherein the door.

[Action]

The control means defines whether the cascade connection output terminal, the coincidence signal output terminal and the multiple coincidence signal output terminal are active or inactive according to whether the cascade connection input terminal is active or inactive. Therefore, when performing cascade connection, the cascade connection input terminal of the first symbol string matching memory is grounded and made inactive, and the cascade connection output terminal is connected to the cascade input terminal of the second symbol string matching memory. To do. In this case, when a match occurs in the first memory, the cascade connection input terminal of the second memory becomes active, and the match signal output terminal thereof generates a match signal and becomes inactive. Becomes active.

As a result, if a coincidence signal is generated in both the first and second memories, the coincidence signal output terminal of the first memory is active, the multiple coincidence signal output terminal is inactive, the coincidence signal of the second memory is coincident. The signal output terminal becomes inactive, and the multiplexed signal output terminal becomes active.

Therefore, the logical state of each coincidence signal output terminal and each multiple coincidence signal terminal, for example, the coincidence signal is comprehensively judged by the priority encoder, and the multiple coincidence signal is comprehensively judged by the OR gate. You can get the output and its address code.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a symbol string matching memory of the present invention. The symbol string matching memory according to the present embodiment stores a finite length shift register 13 that shifts a plurality of n data input from the data input terminal 11 by an external clock input from the clock input terminal 12, and a plurality of addresses. Each address has storage means of the same scale as the shift register 13, and the contents of the shift register 13 and the contents stored in the storage means at all addresses are compared in parallel to determine whether or not each address matches. An associative memory 14 as a storage comparison unit that outputs the comparison result signal 26 shown, a match signal 27 when the comparison result signal 26 is input and a match exists, and a multiple match signal 28 when a plurality of matches exist, Address code of the storage means that encodes the comparison result signal 26 and agrees
Priority encoder 15 for outputting 29, and match signal output terminal 16 for outputting match signal 27, multiplex match signal 28 and address code 29, multiplex match signal output terminal
17 and address code output terminal 18, cascade connection input terminal 19, cascade connection output terminal 25, and cascade connection input terminal 19 when active input,
The match signal output terminal 16 is inactive regardless of the output of the match signal 27, the cascade connection output terminal 25 is active, and when the cascade connection input terminal 19 is inactive input, the cascade connection output terminal 25 is the match signal 27. Is output when is output, and inactive when not output.

The control means 20 has one input connected to the cascade connection input terminal 19 and the output connected to the cascade connection output terminal.
OR gate 21 of 2 inputs connected to 25, and one inverting input is connected to one input of OR gate 21, the other input is connected to match signal 27, and the output is the other input of OR gate 21 and match signal output terminal 16 A two-input AND gate 22 connected to, and one input connected to one inverting input of the AND gate 22 and the other input connected to the match signal 27.
AND gate 23 for input and AND gate 23 for one input
Of the two inputs and the other input to the multiplex coincidence signal 28 and the output to the multiplex signal output terminal 17. In this embodiment, the case of active "H" is shown.

The feature of the present invention is that in FIG. 1, an input terminal 19 for cascade connection, an output terminal 25 for cascade connection, and a control means are provided.
20 and 20 and are connected as shown.

Next, the operation of this embodiment will be described. First, the logical operation of the control means 20 will be described. Table 2 shows a truth table of logical operations. That is, the control means 20 performs the control operation as follows.

When the cascade connection input terminal 19 is active, the match signal output terminal 16 is inactive, and the multiple signal output terminal 17 is Active when a match signal is output, inactive when a match signal is not output, • Cascade connection output terminal 25 is active.

When the cascade connection input terminal 19 is inactive, the match signal output terminal 16 is active when the match signal is output, inactive when the match signal is not output, and the multiple match signal output terminal 17 is the multiple match signal output Is active, otherwise is inactive, ・ The output terminal 25 for cascade connection is active when a match signal is output, and inactive otherwise.

When an external clock is input from the external clock input terminal 12 and data synchronized with it is input from the data input terminal 11, the shift register 13 and all pattern symbol strings registered in advance in the associative memory 14 are compared in parallel in real time. Then, the comparison result signal 26 is output. Then, one signal line that is an input of the priority encoder 15 is activated corresponding to the address where the coincidence occurs. The output from the priority encoder 15 is controlled by the control means 20.When the cascade connection input terminal 19 is active, the match signal output terminal 16 becomes inactive regardless of the all match signals from the associative memory 14, and the multiple match signal output. The terminal 17 is inactive only when a match does not occur in the associative memory 14, and is active otherwise. When the cascade connection input terminal 19 is inactive, the associative memory
When a match occurs at 14, the match signal output terminal 16 becomes active, and only when a plurality of matches occur, the multiple match signal output terminal 17 becomes active. The cascade connection output terminal 25 becomes active when the cascade connection input terminal 19 is active or when the match signal output terminal 16 is active.

FIG. 2 is a block diagram showing an embodiment of a cascade connection system of the symbol string collation memories of the present invention, in which two cascade connectable symbol string collation memories of the present invention shown in FIG. 1 are cascade-connected. Is. In the present embodiment, the first symbol string matching memory 31 including the associative memory 32, the second symbol string matching memory 33 including the associative memory 34, and the inputs of the first and second symbol string matching memories 31 and 33 are respectively connected. The data bus 35 and the clock signal line 36, the ground line 37 for fixing the cascade connection input terminal 19 of the first symbol string collation memory 31 inactive, and the first symbol string collation memory 31.
Output terminal 25 for cascade connection and second symbol string collation memory
A signal line 38 connecting the input terminal 19 for cascade connection of 33,
A bus 39 in which matching address code outputs of the first and second symbol string matching memories 31 and 33 are multi-connected, and an input is a matching signal output terminal 16 and a signal line 41 of the first and second symbol string matching memories 31 and 33. Priority encoder 40 connected by 42 and one input is the first symbol string matching memory 31
Multiple coincidence signal output terminal 17 is connected to the signal line 44, and the other input is the second coincidence signal collation memory 33 multiple coincidence signal output terminal.
OR gate 43 connected to 17 by signal line 45, and OR gate
An output signal line 46 indicating a multiple match with at least one of the first and second symbol string matching memories 31 and 33 connected to the output of 43 and cascaded, a match address code output bus 39, and a priority encoder 40. And an output bus 47 indicating the matching address code through two of the associative memories 32 and 34.

The feature of the present invention is that in FIG. 2, the first symbol string collation memory 31 and the second symbol string collation memory 32 are connected as shown in the same figure by using the priority encoder 40 and the OR gate 43. is there.

Next, the operation of this embodiment will be described. The pattern symbol strings “ABCDEF” and “XYZ” are assigned to the addresses “00” and “01” in the associative memory 32, and the address “0” in the associative memory 34.
Pattern symbols "OPQRSTU" for "0" and "01" respectively
Register "XYZ" in advance. Clock signal line 36
When the collation symbol string "ABCDEF" is input from the external clock and the data bus 35 in synchronization with the clock, a match occurs in the associative memory 32, and the match address code "00", signal line 38 and 41 is an active output, and the match address code "000" is output to the output bus 47.

At this time, the signal lines 44, 42 and 45 are inactive outputs,
The address code output terminal 18 of the symbol string collation memory 33 has high impedance. Similarly, when the collation symbol string "OPQRSTU" is input from the data bus 35, a match occurs in the associative memory 34, the match address code "00" is output to the bus 39, and the signal line 42 becomes an active output and is output. bus
47 becomes "100". At this time, the signal lines 38, 41, 44 and 45 are inactive output, and the address code output terminal 18 of the first symbol string collation memory 31 has high impedance.

Next, in the same way, from the data bus 35, collation symbol string "XYZ"
Is input in synchronization with the external clock from the clock signal line 36, a match occurs in both the associative memories 32 and 34. At this time, the bus 39 has the coincident address code “01”, and the signal lines 41 and 38 are active outputs. Associative memory because signal line 38 for cascade connection is active
Despite the coincidence at 34, the signal line 42 becomes inactive, and the address code output terminal 18 of the symbol string matching memory 33 becomes high impedance. Further, although the signal line 44 is inactive, the signal line 45 becomes an active output, and the output signal line 46 also becomes active, and multiple coincidence occurs in the cascade-connected first and second symbol string collation memories 31 and 33. I understand.

In the embodiment of the connection system described above, the case where two symbol string collation memories are cascade-connected is shown, but even if the number of symbol string collation memories is three or more, they can be sequentially cascade-connected like the second symbol string collation memory. it can.

Further, although all of the above explanations have been made active "H", the same applies to the case of active "L" by reversing the logic.

〔The invention's effect〕

As described above, according to the present invention, it is possible to cascade-connect a plurality of symbol string collation memories by including the above-mentioned means, and in this case, the CPU can provide a single large-capacity associative memory with an expanded capacity. It looks like a capacity symbol string matching memory, and has the effect of easily expanding the registered pattern capacity.
In addition, the occurrence of multiple coincidences across a plurality of LSI chips can be easily detected.

[Brief description of drawings]

FIG. 1 is a block diagram showing the first embodiment of a symbol string matching memory of the present invention. FIG. 2 is a block diagram showing a second embodiment of the cascade connection system of the symbol string matching memory of the present invention. FIG. 3 is a block diagram showing a conventional symbol string matching memory. FIG. 4 is an explanatory diagram of the priority encoder. 11 …… Data input terminal, 12 …… External clock input terminal,
13 …… Shift register, 14, 32, 34 …… Associative memory, 1
5, 40 …… Priority encoder (PECD), 16 ……
Matching signal output terminal, 17 ... Multiplex matching signal output terminal, 18 ...
... Address code output terminal, 19 ... Cascade connection input terminal, 20 ... Control means, 21, 24, 43 ... OR gate,
22、23 …… AND gate, 25 …… Cascade connection output terminal, 31,33 …… Symbol collation memory, 35 …… Data bus, 36 …… Clock signal line, 37 …… Grounding wire, 38,41, Four
2,44,45 …… Signal line, 39 …… Bus, 46 …… Output signal line, 47 …… Output bus.

Claims (2)

[Claims] 1. A shift register (13) which is operated by an external clock, and a storage means having a plurality of addresses, each address having the same scale as the shift register, and the contents of the shift register and the storage at all addresses. Storage comparison means (14) for comparing the contents stored in the means in parallel and outputting a comparison result signal indicating whether or not there is a match for each address; and when there is a match when the comparison result signal is input. A priority encoder (1) that outputs a coincidence signal, a multiple coincidence signal when a plurality of coincidences exist, and the address code of the storage means that encodes the comparison result signal and coincides with each other.
5), and a symbol string matching memory including a match signal output terminal (16) for outputting the match signal, the multiple match signal and the address code, a multiple match signal output terminal (17) and an address code output terminal (18), respectively. In the above, a cascade connection input terminal (19) and a cascade connection output terminal (25) are provided, and when the cascade connection input terminal is an active input, the match signal output terminal is irrespective of the output of the match signal. No inactive, the cascade connection output terminal is active, the multiplex match signal output terminal is active when the match signal is output, inactive when not output, the cascade connection input terminal is inactive In the case of input, the output terminal for cascade connection is an output terminal when the coincidence signal is being output. The symbol string collation memory is equipped with a control means (20) for controlling each active and inactive when not being output. 2. A shift register operated by an external clock, and a storage means having a plurality of addresses, each address having the same scale as the shift register, and storing the contents of the shift register and the storage means at all addresses. The stored contents are compared in parallel with each other to output a comparison result signal indicating whether or not there is a match for each address, and a match signal when the comparison result signal is input and a match is found, a match is made. A priority encoder that outputs a multiple coincidence signal when a plurality of them exist, and outputs the address code of the storage means that encodes and compares the comparison result signal, and a coincidence signal that outputs the coincidence signal, the multiple coincidence signal, and the address code, respectively. Output terminal, multiple coincidence signal output terminal and address code output terminal, cascade connection input terminal, When the connection connection output terminal and the cascade connection input terminal are active inputs, the match signal output terminal is inactive regardless of the output of the match signal, the cascade connection output terminal is active, and the multiple match The signal output terminal is active when the match signal is output, inactive when not output, and when the cascade connection input terminal is inactive, the output signal for cascade connection outputs the match signal A plurality of symbol string collation memories each having a control means for controlling each of the symbol string collation memories (31) to be active when it is not being output, and to be inactive when not being output, and the cascade connection input terminal of the first symbol string collation memory (31). And the output terminals for cascade connection are a ground potential and a second symbol string matching memory, respectively. 33) is connected to the cascade connection input terminal, and the coincidence signal output terminals of the first and second symbol string collation memories are connected to the inputs of the second priority encoder (40), respectively, and the multiple signal output is connected. Each terminal is connected to an input of a logic circuit (43) for performing a predetermined logical operation, and the address code output terminal is commonly connected to one bus (47) together with the output of the second priority encoder,
The output of the logic circuit is connected to the multiple coincidence output signal line (46), and the third, fourth, ... Symbol string matching memories are connected in the same manner. Cascade connection of symbol string matching memories. method.