JPH0550078B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an associative memory device, that is, a memory device that can perform addressing based on stored contents.

(Prior art and its problems) This type of associative memory device is an important device used as a component of an electronic computer. An example of the application of associative memory is ``Ultra-high-performance electronic computers using large-scale projects'' (edited by the Agency of Industrial Science and Technology, Ministry of International Trade and Industry,
Published by Japan Industrial Technology Promotion Association (July 1947)
Mentioned in PP45-48. According to this, the associative memory device stores which address of the main memory device corresponds to the selector of the buffer memory, and makes it possible to perform address conversion from a logical address to a physical address at high speed by searching the contents.
Also, Nikkei Electronics (published on October 27, 1980)
Pages 102 to 136 include list processing, image processing,
Applications to databases are described.

Regarding the associative memory elements used in this type of associative memory device, there are already many references, such as ``logical memory'' published in ``Information Processing Handbook''.
(Published by Ohmsha in May 1947, edited by Information Processing Society of Japan,
It is introduced in PP13-96-PP13-99).
According to this, this type of associative memory device requires an associative memory element having a configuration in which each memory element that can store information is provided with a coincidence detection circuit that checks whether the stored content matches the search information. Therefore, compared to memory elements used in ordinary memory devices that are accessed by supplying an address indicating the storage location of desired data, conventional associative memory elements have a more complex structure.
It had the disadvantage that the cost per bit was several tens of times higher.

In order to eliminate this drawback, an associative memory device has been considered in which a normal memory element is used in the information storage section and a match detection circuit is provided for each word. However, this associative memory device has a drawback in that it requires a number of search operations corresponding to the number of bits.

Furthermore, a first normal storage element which takes the search information as an address input and stores data information, and a second normal storage element which takes the data information or the read output of the first normal storage element as an address input and stores the search information. An associative memory device using memory elements was published in Japanese Patent Application Laid-open No.
No. 49-73039. However, although this associative memory device has the advantage of being able to be constructed using ordinary memory elements, as the number of bits of search information or data information increases, the number of memory elements required increases significantly, resulting in an increase in price. have.

(Object of the Invention) The present invention easily solves the above-mentioned conventional drawbacks and provides a high-speed, large-capacity, and low-cost associative memory device that is composed of ordinary memory elements that are accessed by supplying addresses. It is in.

Another object of the present invention is to provide an associative memory device capable of performing a search operation while masking a portion of search information.

Furthermore, another object of the present invention is to provide an associative memory device that can tolerate some errors in search information.

(Structure of the Invention) Therefore, according to the present invention, the following content addressable memory device is obtained.

A first storage means that takes input data as an address input and stores data specified by the input data that differs only in word in the bit specified by the write address, and stores input data at the time of registration in the word specified by the write address. a selection circuit which receives the input data and the read output of the second storage means and selectively supplies one of them to the address input of the first storage means; a write decoder that controls writing to the bit specified by the write address of the first storage means; a temporary storage means that takes in the read signal of the first storage means; an encoder connected to the output of the first storage means; an associative memory device characterized by comprising: a decoding means for resetting the storage means; a search information modulation means for generating input data by modulating a part of primary data supplied from the outside; A first storage means that inputs an address and stores data that differs only in the word specified by the input data in the bit specified by the write address, and writes to the bit position of the first storage means specified by the write address. temporary storage means for receiving a read signal from the first storage means; encoding means connected to this output; and decoding means using this output as an input and resetting the temporary storage means. It is a characteristic associative memory device.

(Example) Hereinafter, the present invention will be explained in more detail using the drawings.

FIG. 1 shows a configuration diagram of an example of an associative memory device according to the present invention. This associative memory device has input data 10
1 as an input and outputs a search address in which data matching the input data is stored. Writing means 1 for storing the decoding result of input data 101 in the bit position of means 110
50 and each read signal 1 of the first storage means 110
A register 120 that takes in 02 and a register 120
It consists of an encoder 130 that outputs a search address 131 indicating a bit position whose content is "1", and a decoder 140 that resets the bit of the register 120 specified by the search address 131. The register 120, encoder 130, and decoder 140 are temporary storage means, encoding means, and
Corresponds to decoding means.

The first storage means 110 is constituted by a conventional storage element that is accessed by providing an address indicating the storage location of desired data. Assuming that the memory structure of this content addressable memory device is N words and M bits, the number of memory cells of the first memory means 110 is 2M words and N bits.
The number of bits of the input data 101 is M
Becomes a bit. Also, the number of bits in the register 120, the number of input bits in the encoder 130, and the number of input bits in the decoder 1
The number of output bits of the 40 bits is N bits each, and the output of the encoder 130 or the decoder 140
The number of bits of the search address 131, which is the input of
log ₂ N.

This content addressable memory device performs three operations: registration, deletion, and search. Input data 101 is given as registration information during a registration operation, and is given as search information during a search operation. Below is the first storage means 1
The registration operation, deletion operation, and search operation will be sequentially explained starting from a state in which all contents of 10 are cleared to "0".

In the registration operation, a write address 151, a registration/deletion signal 152 of "1", and a write pulse signal 153 are given to the writing means 150, and the registration information is stored as input data 101 in the first storage means 1.
given to 10. The registration/deletion signal 152 selects a registration operation and a deletion operation by "1" and "0", respectively. The first storage means 110 has registered information 1
01, access to the word specified by the registration information 101 is permitted. In this state, the writing means 150 writes the first address designated by the write address 151.
A write control signal 154 is applied so as to write "1" indicated by the registration/deletion signal 152 to the bit position of the storage means 110. As a result, "1" is stored in the bit designated by the registration information 101 and the write address 151 of the first storage means 110. In other words, the registration information 101 has a bit pattern in which only the address specified by it is "1".
is stored in the storage means 110 of. This bit pattern is equal to the decoding result of registration information 101.

Similarly, the deletion operation can be performed in the same way as the registration operation by giving a registration/deletion signal 152 of "0" to the writing means 150 so as to store the bit "0" specified by the write address 151 of the first storage means 110. It is done. By this deletion operation, the contents of all addresses at the bit positions specified by the write address 151 of the first storage means 110 are cleared to "0".

To explain the search operation, the previously explained registration operation stores registered information A,
B, C, I are write addresses 0, 1, 2, j respectively
It is assumed that it is registered at the address specified in . That is, "1" is stored only at address A of the 0th bit, address B of the first bit, address C of the second bit, and address I of the jth bit of the first storage means 110. In the search operation, when A, B, C, and I are given as input data 101, it is necessary to output 0, 1, 2, and j as search addresses 131, respectively.

First, when search information A is given as input data 101, the contents of address A of first storage means 110 are output as read signal 102. If the previously registered registration data A, B, C, and I are different from each other, this read signal 102 is the 0th read signal 102.
Only the bit becomes “1”. The read signal 102 is taken into the register 120 by a search clock signal 121 given in synchronization with the search information 101.
The signal is supplied to the encoder 130. Encoder 13
For input of 0, only the 0th bit is "1". “1”
An input that is , means that data matching the search information A is registered in the associative recording device. If the encoder 130 has a "1" input, it outputs the bit position of the "1" input together with a match signal 132 as a search address 131. In this case, since only the input of the 0th bit of the encoder 130 is "1", the search address becomes 0.
That is, the address where the search information A is stored is output as the search address 131. After reading the search address 131, an external device such as a processor provides a reset signal 141 to the decoder 140. Decoder 140 supplies a reset signal 141 to the reset input of the bit specified by search address 131 in register 120, changing the content of that bit from "1" to "0". If there is only one piece of data matching search information A, match signal 1
32 stops occurring, and the search operation is also completed.

However, at the time of multiple matches when a plurality of data matching the search information A are registered, the encoder 130 further generates a match signal 132 and a search address 131 indicating the storage address of the next matching data. In this case, the external device repeatedly reads the search address 131 and sends the reset signal 141 until the match signal 132 is no longer generated.
By giving , all search addresses 131 that match the search information can be found.

FIG. 2 is an explanatory diagram of an embodiment of the writing means 150 used in the associative memory device of FIG. 1. This writing means is composed of a writing decoder 210,
Write write pulse signal 153 to write address 151
Write enable signal 211 for the bit position specified by
lead as. The registration/deletion signal 152 and the write permission signal 211 are supplied as a write control signal 154 to each bit of the first storage means 110 in FIG. The registration/deletion signal 152 is transmitted to the first storage means 11
The write data will be 0, and it will become “1” during registration operation.
It becomes "0" during the deletion operation.

By this writing means, write address 151
The data indicated by the registration/deletion signal 152 can be stored in the first storage means 110 designated by .

FIG. 3 is an explanatory diagram of another embodiment of the writing means 150 used in the associative memory device of FIG. 1. This write means is composed of a write decoder 210, an OR gate 310, and a switch 320, and receives a write address 151, a registration/deletion signal 152, and a write pulse signal 153 to enable writing to the first storage means 110 in FIG. Signal 211 and bit power supply 321 are supplied as write control signal 154. The bit power supply 321 serves as a power supply for each bit of the first storage means 110.
The contents of the bits in the first storage means 110 whose supply of bits 21 is temporarily stopped are cleared to "0".
To this end, the first storage means 110 is a static transistor in which a flip-flop of storage cells is constructed of transistors having different switching speeds.
It consists of RAM and dynamic RAM whose storage cells are discharged when the power is turned off. This bit power supply is turned on and off by a switch 320. A power supply 322 and the output of the OR gate 310 are connected to each switch 320 . Switch 320 connected to the output of OR gate 310 of “0”
prohibits the currency of power supply 322, bit power supply 321
cut.

When performing a deletion operation, register “0” to indicate the deletion operation.
Delete signal 152 and negative pulse write pulse signal 1
53 and write address 151 are supplied. Write decoder 210 directs write pulse signal 153 to the bit position designated by write address 151 as write enable signal 211. This write permission signal 211 disconnects the switch 310 via the OR gate 310. Therefore, the bit power supply 32 at the bit position specified by the write address 151
1 is disconnected, and the contents of all addresses of bits specified by the write address 151 of the first storage means 110 are cleared to "0". That is, a deletion operation is performed.

The registration operation is performed in pair with the deletion operation.
First, the registration operation is a deletion operation to delete already registered data, then the registration/deletion signal 152 is returned to "1", and the write pulse signal 153 is given to the decoder 210 again. When the write pulse signal 153 is supplied again, the bit power supply 321 is supplied to all bits of the first storage means 110, and the bit power supply 321 is supplied to all bits of the first storage means 110 specified by the write address 151.
A write enable signal 211 is applied to the 0 bit. By always giving "1" as write data to the first storage means 110, "1" is set to the bit specified by the write address 151 of the address specified by the input data 101 of the first storage means 110. is written. In this way, the input data 101 given as registration information can be registered.

This writing means does not need to provide already registered data as input data 101 in the registration or deletion operation, making it possible to realize an easier-to-use associative memory device.

FIG. 4 is an explanatory diagram of another embodiment of the writing means 150 used in the associative memory device of FIG. 1. FIG. 4 also shows the overall configuration of the associative memory device in order to make it easier to understand the connection relationship between the writing means 150 and other components surrounded by broken lines. This writing means uses the write address 151 as an address input, and the second storage means 410 stores the input data 101.
The input data 101 and the registered data 411 which is the read output of the second storage means 410 are input, and one of them is selectively supplied to the address input of the first storage means 110 by the registration/deletion signal 152. and a selection circuit 420. The memory structure of the associative memory device shown in FIG.
If it is a bit, then the storage structure of the second storage means 410 will also be N words and M bits.

During the registration operation, the content "1" is stored in the first storage means 1 in a format expressed by an address stored therein.
The registration information stored in each of the 10 bits is also stored in the address of the second storage means 410 corresponding to each bit of the first storage means 110. for example,
When registered data A, B, C, and I are registered at the addresses specified by write addresses 0, 1, 2, and j, respectively, the first storage means 110 stores the A address of the 0th bit, “1” is stored only in the first bit at address B, the second bit at address C, and the jth bit at address I, and the second storage means 410 stores 0, 1,
A, B, C, and I are stored at addresses 2 and j, respectively.

That is, by applying the registration/deletion signal 152 of "1" and performing the same registration operation as the associative memory device of FIG. 1, the registration information is stored in the first storage means,
Furthermore, the write address 1 of the second storage means 410
Input data 101 serving as registration information is stored at the address specified by 51. As a result, a registration operation is performed. Note that the registered data that is the content of the second storage means 410 is used in the deletion operation described below.

In the deletion operation, the registration/deletion signal 152 of "0" is given, and the contents of the second storage means 410 indicated by the write address 151, that is, the registered data 41
1 to the address input of the first storage means 110. Furthermore, by supplying the write pulse signal 153 to the write decoder 210 in the same manner as the deletion operation of the content addressable memory device shown in FIG.
The content "1" of the bit indicated by the write address 151 of 0 is rewritten to "0" and the registered data is deleted.

Note that during the registration operation, it is first necessary to perform this deletion operation in order to erase the registered data.

This associative memory device does not require the provision of registered data from an external device, which was necessary for the deletion operation of the associative memory device of FIG. 1 using the writing means of FIG. Easily register registered data by outputting the output externally 4
11 can be confirmed.

FIG. 5 is an explanatory diagram of an embodiment of an associative memory device according to the second invention. This associative memory is the first
It is possible to handle search information with a larger number of bits than the associative memory device shown in FIGS. For this reason, an AND gate 510 serving as a logical product means, an OR gate 520 serving as a masking means, and a counter 530 serving as a counting means are added to the associative memory device shown in FIG. 1 using the writing means shown in FIGS. 2 and 3. ing.

The memory structure of this associative memory device is N words M×K
If it is a bit, then the storage structure of the first storage means 110 is ^2M ×K words and N bits, and the counter 53
The number of zero bits is log ₂ K bits. Therefore, assuming that the first storage means 110 of ^2M words in FIG. 1 is a block, the first storage means 110 is as follows.
Consists of K block. The 0th block has addresses 0 to 2 ^M -1, and the K-1st block has addresses (K
-1) The address range is from ×2 ^M to K ×2 ^M -1.
Block designation is performed by counter 530. The search information and registration information of M×K bits are divided into 101K pieces of input data of M bits and sent to the first storage means 110. K input data 10
The registration information sent in step 1 is stored in each block of the first storage means 110 for each input data 101.
For example, four M-bit data A ₀ , A ₁ , A ₂ , A ₃
In the registration information A, only the address A0 of the 0th block of the first storage means 110, the address _A1 of the first block, the address _A2 of the second block, and the address _A3 of the third block are set to "1" _. It is stored in the same state.

The registration operation, deletion operation, and search operation will be explained in more detail.

First, the four M-bit data A ₀ shown above,
A registration operation for registering registration information A consisting of A ₁ , A ₂ , and A ₃ to address J will be described. In the case of a registration operation, a counter clear signal 531 is sent to the associative memory device.
and registration/deletion signal 152 of “1” indicating registration operation.
First, the write address 151 of address J is supplied. As a result, the contents of the counter 530 are cleared and the 0th block of the first storage means 110 is designated.

Next, when data A ₀ , which is part of the registration information A, is supplied as input data 101 and a search clock signal 121 of a negative pulse signal and a write pulse signal 153 are supplied, the Jth bit of the first storage means 110 is “1” in address A ₀ of 0th block
is stored. Since the contents of counter 530 are incremented at the rising edge of search clock signal 121, counter 530 specifies the first block after this operation is completed. Data as input data 101
When this operation is executed three times by changing A ₁ , A ₂ , and A ₃ , the J-th bit of the first storage means has the address A ₀ of the 0th block, the address A ₁ of the first block, and the address of the second block. A ₂ and "1" are stored only in address A ₃ of the third block.

As described above, by registering input data 101 four times in total, registered information A consisting of data A ₀ , A ₁ , A ₂ , A ₃
The registration operation is completed.

The deletion operation is performed in the same manner as the registration operation by further supplying a registration/deletion signal 152 of "0" and a write pulse signal 153. That is, the contents of all bit addresses specified by the write address 151 of the first storage means 110 become "0".

Next, the operation when a search is performed using the same search information A in a state where registration information A is registered at address J will be described. This associative memory device is capable of performing a search operation by masking part of the search information. First, a search operation in which a mask signal 532 of "0" is supplied and no mask processing is performed will be described.

A counter clear signal 531 is supplied during the search operation. The counter clear signal 531 clears the contents of the counter 530 and also clears the contents of the register 12.
Set the contents of all 0 bits to "1". Next, data _A0 , which is part of the search information A, is supplied as input data 101, and a search clock signal 121 of a negative pulse signal is also supplied. counter 530
specifies the 0th block, the read signal 102 of the first storage device 110 becomes the contents of address _A0 of the 0th block. Therefore, the J-th read signal 102 is at least "1".
The contents of all bits in the register 120 are set to "1", and the mask signal 532 is "0".
Since the read signal 102 is supplied with
Incorporated into 0. The register 120 whose all bits were set to "1" is now set to the register 120 corresponding to the bit that stores the data _A0 as part of the registration information in the 0th block of the first storage means 110.
Only the bit ``1'' is held, and the other bits change to ``0''. Here, at least register 1
The content of the J-th bit of 20 is “1” which means a match.
shows. Also, the counter 530 increases by 1,
The first block of the first storage means 110 is specified.

Furthermore, data that is the remaining part of search information A
When A ₁ , A ₂ , and A ₃ are applied together with the search clock signal 121 as input data 101, the contents of the bits of the register 120 corresponding to the bits of the first storage means 110 storing registered information that does not match the search information is reset to "0". Therefore,
Registration information A, which is equivalent to search information A, is registered in the bit of the first storage means 110 that corresponds to the bit of the register 120 that holds "1". If registration information A is registered at address J in the content addressable memory device, the Jth bit of register 120 remains as "1".

The encoder 130 encodes the contents of the register 120 in the same way as the content addressable memory shown in FIG. Furthermore, if a plurality of data matching the same search information are registered, the contents of the plurality of bits in the register 120 become "1" indicating matching. The encoder 130 outputs the lower bit number therein as a search address 131, and the decoder 140 outputs the output search address 1.
Set the bit of register 120 corresponding to 31 to “0”
Reset to . As a result, the encoder 130
The search address 131 is generated sequentially from the lower bit numbers of the register 120 which is set to "1".

In this way, a search operation is performed without masking. Masking of the search information is performed in units of input data 101, and is easily accomplished by applying a mask signal 532 of "1" when a part of the search information to be masked is applied as input data 101. When the mask signal 532 of "1" is applied, the output of the OR gate 520 becomes "1" regardless of the read signal 102, and the input data 101 at that time is ignored. Therefore, part of the search information is masked.

As explained above, according to the present invention, an associative memory device of N words M x K bits can be stored as 2 ^M x K words N
It can be constructed using a conventional first storage means 110 of bits. In the associative memory shown in Figure 1, the first
Compared to the case where a normal memory element of 2 ^M×K words and N bits is required as the memory means 110 of , the associative memory device of FIG.
Bringing low prices. Further, it is possible to perform a search operation by masking part of the search information.

FIG. 6 is an explanatory diagram of an embodiment of an associative memory device according to the third invention. This associative memory is the first
Compared to the associative memory device shown in Fig. 4, it is possible to handle search information and registration information with a larger number of bits, and to perform search operations by masking part of the search information. Search operations and registration operations can be performed faster than in comparison. For this reason, the associative memory device shown in FIG. 1 is provided with an AND gate 610 and a plurality of first storage means 110.

The memory structure of this associative memory device is N words M×K
If it is a bit, the storage configuration of each first storage means is
2 ^M words and N bits, and the first storage means 1
The number of 10s is K. The number of bits of the associative memory device shown in FIG. 5 is expanded by increasing the number of words of the first storage means 110; . The block of the first storage means 110 in the associative memory device of FIG. 5 corresponds to each first storage means 110 in this associative memory device. M
The search information and registration information of ×K bits are divided into K pieces of M-bit input data 101, each of which is supplied to K pieces of first storage means 110 in parallel. The registration information supplied by the K pieces of input data 101 is stored in a format in which only the address specified by the input data 101 of each first storage means 110 is set to "1" for each input data 101. For example, registration information A consisting of three M-bit data A ₀ , A ₁ , A ₂ is the 0th
Address A ₀ of the first storage means 110, address A ₁ of the first storage means 110, and address A ₂ of the second storage means 110.
It is stored by setting only "1" to "1". The bit number of the first storage means 110 to be stored is designated by the write address 151. This writing is controlled by the writing means 150 shown in FIG. 2, 3, or 4.

In a search operation using search information A that is the same as registered data, data A ₀ , which constitutes search information A,
A ₁ and A ₂ are supplied as each input data 101 to each first storage means 110 . Each first storage means 1
The read signal 102 from 10 is routed bit by bit to AND gate 610. Each output of the AND gate 610 is connected to each first storage means 110.
The result of matching is "1" or "0" indicating whether the registration information stored in each bit matches the given search information A or not. Assuming that registration information A matching search information A is stored at the J-th bit of each first storage means 110, the output of the J-th AND gate 610 indicates "1". and gate 6
The output of 10, ie, the matching result, is loaded into register 120 by search clock signal 121. Thereafter, the search address 13 is stored via the encoder 130 similarly to the associative memory devices shown in FIGS.
1 is required.

The K mask signals 532 are used for masking search information in units of M bits. Mask signal 53
When 2 is input, the read signal 102 of the first storage means 110 connected to that signal is forced to "1".
be made into Therefore, the input mask signal 532
A part of the search information corresponding to is masked, and a search operation can be performed while masking part of the search information.

As explained above, this associative memory device can configure an N word M×K bit associative memory device by using K first storage means 110 of 2M ^words and N bits, and its search operation and registration operation can be performed. This can be done by accessing the first storage means 110 once, and high-speed operation is possible. It is also possible to perform a search operation by masking part of the search information.

Note that write address 151 and search address 1
31 in common, or by providing a register for each of the plurality of input data 101 shown in FIG. 6 and connecting them to a common input line, it is also possible to reduce the number of input/output pins.

FIG. 7 is an explanatory diagram of an embodiment of an associative memory device according to the fourth invention. This associative memory device is a flexible associative memory device that allows searching that tolerates a one-bit error in the given search information.
A search for inputting primary data 721 given from an associative memory unit 710 corresponding to the associative memory device shown in FIG. 4, FIG. 5, or FIG. 6 and an external device, and supplying input data 101 to the associative memory unit 710. and information conversion means 720.

Primary data 721 given from the outside is converted to search information converting means 720 by set pulse signal 722.
is stored in When a conversion signal 723 of “0” is applied, the stored primary data 721 is applied as is to the associative memory unit 710 as input data 101, and when a conversion signal 723 of “1” is applied, 1 in the stored primary data 721 is applied. The bits are changed and output as input data 101. The bit positions to be converted start from the least significant bit and move to the more significant bits each time shift pulse signal 724 is applied.

The registration operation, the deletion operation, and the search operation by applying the primary data 721 as is to the input data 101 are the same as the operations of the associative memory device shown in FIG. 1, FIG. 4, FIG. 5, or FIG. 6.

In the search operation for search information that differs from the primary data 721 by 1 bit, a conversion signal 723 of "1" is supplied, and data obtained by changing the least significant bit of the primary data 721 is first supplied to the associative memory unit 710 as input data 101. Let's do it. As a result, a search operation is performed for the search information in which the least significant bit of the primary data 721 is different, and the search address 131 that is the storage address thereof is determined.

Next, a shift pulse signal 724 is supplied, the bit position to be changed in the primary data 721 is shifted by one bit, and the input data 101 is supplied to the associative memory section 710.

By repeating the above search operation, the search operation is performed for all search information that differs from the primary data 721 by 1 bit. That is, a search operation is possible for data that is separated by a Hamming distance of 1 from the primary data 721.

FIG. 8 shows the search information conversion means 72 shown in FIG.
0 is an explanatory diagram of one embodiment of the invention. This search information conversion means converts the primary data 721 into a set pulse signal 72.
2, the data register 810 is taken in, and only the least significant bit is set to “1” by the set pulse signal 722.
The shift register 82 is initially set to the contents of
0, shift register 820 and data register 8
10 and an exclusive OR gate 830 which receives the output of 10 and generates input data 101.

The shift register 820 receives the “0” conversion signal 72
When receiving 3, all outputs are set to “0” and set to “1”.
The contents are output only when the conversion signal 723 is received. Therefore, when the conversion signal 723 of "0" is supplied, the primary data 721 stored in the data register 810 is outputted as input data 101 as is. When the conversion signal 723 of “1” is supplied,
The output of the data register 810 corresponding to the bit whose contents indicate "1" in the shift register 820 is inverted and output as input data 101. The contents of the shift register 820 are the shift pulse signal 724
The bits are shifted upward (to the right) one bit at a time. Therefore, each time the shift pulse signal 724 is applied, the input data 101 in which the bit position to be inverted is shifted upward is output. That is,
Input data 101 that is separated from primary data 721 by a Hamming distance of 1 can be generated.

Note that by limiting the bits to be inverted in the primary data 721 to specific bits, it is possible to mask the search information bit by bit.

(Effects of the Invention) As explained above, the content addressable memory device according to the present invention can be constructed using an inexpensive ordinary memory element that is accessed by supplying an address indicating the storage location of desired data. The associative memory device of FIG. 1 or FIG. 4, which has N words and M bits, can be constructed with a normal memory element of 2 ^M words and N bits as the first storage means 110, and the associative memory device of FIG. 5 or FIG. The associative memory device in Figure 6 has 2 ^M × K words N
It can be constructed of K conventional storage elements of 2 ^M words and N bits. Therefore,
If 256K bit RAM semiconductor technology is used, for example, the associative memory device shown in Figure 1 with 1 kiloword and 8 bits, or the associative memory device shown in Figures 5 and 6 with 1 kiloword and 24 bits can be realized on a single chip. . Generally available semiconductor associative memory,
For example, the content addressable memory IC8220 manufactured by Signetics has 4 words and 2 bits, but the content addressable memory device according to the present invention can be said to have an extremely large capacity.

In addition, search operations and registration operations in this content addressable memory device can be completed with one or several accesses to the normal storage elements, and are faster than conventional word serial/bit parallel or word parallel/bit serial content addressable memory devices. be.

Further, it is possible to perform a search operation by masking a part of the search information, a search operation within a Hamming distance of 1 from the search information, and multiple match processing when matching with a plurality of registered information.

If such a high-speed, large-capacity, low-cost associative memory device is used as a storage device for an information processing system, it will be possible to realize an information processing system that can perform associative processing at high speed in databases, pattern recognition, artificial intelligence, etc. .

In the above description, the AND gate 510 and the OR gate 5 are used as the AND means and the mask means.
Although 20 is used, other logic gates may be used, and this does not limit the scope of the claims of the present invention.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of one embodiment of the associative memory device according to the first invention, FIG. 2 is an explanatory diagram of one embodiment of the writing means, FIG. 3 is an explanatory diagram of another embodiment of the writing means, and FIG. 4 is an explanatory diagram of another embodiment of the first invention,
FIG. 5 is an explanatory diagram of one embodiment of the associative memory device according to the second invention, FIG. 6 is an explanatory diagram of one embodiment of the associative memory device according to the third invention, and FIG. 7 is an explanatory diagram of one embodiment of the associative memory device according to the fourth invention. FIG. 8 is an explanatory diagram of an embodiment of the storage device. FIG. 8 is an explanatory diagram of an embodiment of the search information conversion means used in the associative memory device of FIG. 110...First storage means, 120...Register, 130...Encoder, 140...Decoder, 150...Writing means, 210...Writing decoder, 310, 720...OR gate, 320
...Switch, 410...Second storage means, 42
0... Selection circuit, 510, 610... AND gate, 520... OR gate, 530... Counter, 710... Content addressable memory unit, 720... Search information conversion means, 810... Data register, 820...
...Shift register, 830...Alternative OR gate.

Claims (1)

[Scope of Claims] 1. A first storage means that takes input data as an address input and stores data specified by the input data that differs only in word in the bit specified by the write address, and in the word specified by the write address. a second storage means for storing input data at the time of registration;
a selection circuit which receives the input data and the read output of the second storage means and selectively supplies either one to the address input of the first storage means; and a selection circuit designated by the write address of the first storage means. A write decoder that controls writing to bits, a temporary storage means that takes in a read signal from the first storage means, an encoding means connected to this output, and a decoding means that uses this output as an input and resets the temporary storage means. An associative memory device comprising: 2 search information modulation means for generating input data by modulating a part of primary data supplied from the outside;
A first storage means that takes input data as an address input and stores data that differs only in a word specified by the input data in a bit specified by a write address, and a bit position of the first storage means specified by the write address. A temporary storage means for receiving a read signal from the first storage means, an encoding means connected to the output of the first storage means, and a decoding means for receiving the output and resetting the temporary storage means. An associative memory device characterized by