JPS6059595A - Encoding circuit - Google Patents

Abstract

PURPOSE:To simplify the configuration of an encoder having priority in an associative memory by resetting input side nodes on respective stages corresponding to priority by a switch circuit and impressing a transmission control input to the succeeding step in accordance with an output. CONSTITUTION:A switch S1 is controlled by a clock C1 and a node Q is changed in accordance with its input, an when an input iN is ''1'' and a transmission control input P1 impressed to a switch S6 and an AND circuit A is ''1'', the output OUT is ''1''. Switches S2, S3 are controlled by a clock C2 synchronized with the clock C1 and its inversion clock C3, the node Q is reset to ''0'' in accordance with the ouput OUT and the reset state is not released by the holding function of the switch S2 until the node Q is set by the switch S1. On the other hand, a switch S5 connected to the earth and the switch S6 to which the signal P1 is impressed are actuated in accordance with the state of the contact Q, and only when the input iN is ''0'' and the resetting has been completed, a transmission control input P2 to the succeeding stage is made ''1''. Thus, the input can be encoded without intermediate encoding and the configuration of the encoder with priority is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an associative memory (Content Address
Multiple matching address signals such as sableMemoS: CAM) are encoded in a certain order and converted into binary
This paper provides a simple circuit configuration of a prioritized address encoder used to obtain the address output of , which outputs the address of the word where the data that matches the reference data is stored, but if a match is obtained in multiple words, a normal encoder cannot obtain the correct encoded output ^ In other words, Before applying the signals to a conventional binary encoder, an appropriate order must be applied so that only one signal becomes an ON potential and is sequentially switched and output in synchronization with a clock signal.

The functions that the priority address encoder should have are explained below using FIG. here,? (I I
I I ) is the input signal vector, 3'2'1'
0 0 (031U2,01+00J?1m Koma Deba 1 one side vector, A (A3.A2.A1.Ao) is the final output signal vector or output address 17, input signal priority is I3>I2>I1> ■.Suppose that. On the other hand, c
l is a seven soto terminal, and C2 is a clock signal terminal.

This function first resets the entire system by a signal applied to terminal C1, then clock signal input terminal C2.
Addresses are sequentially output in order of priority in synchronization with a clock signal applied to the address. Here, the conversion from completion to d is performed according to the rules described below.

1. When logic "1" exists in only one place or almost exists in the element of human power signal vector, 2. When logic "1" exists in two or more places in the element of human power signal vector,
For example, the three locations I, , I, and I□ are logical "1",
If i＞+＞k, then 0=(0,...,0,1,O,...O) (1st clock) 1ζ6 pages↑ 6゜5=(o,..., o, i, starvation, O) (second clock) ↑ Φ] 0 = (o,..., 0,1, O,..., 0) (third clock)
(Clock) ↑ (If 5 is set to 1, the output signal vector will contain only one or less logic "1" as an element, and even if there are multiple logic "1"s in the input signal vector elements, The signals are output in order of priority according to the clock signal.

The intermediate output signal vector 0 obtained as above is the first
It is encoded by address encoder Y in the figure.

This encoder is a normal one, and if 5 is logical ``1'', the binary code of i is output.

be done. For example, when A1.01 is a logic "1", that is, the ON potential of the transistor A1. The MOS transistor connected to A2 is turned on, current flows through the load resistors R1 and R2, and the output terminal A4. The potential of A2 decreases and the logic r
Becomes O.J. On the other hand, A. Since the I-1 potential does not fall, the state is "logic 1-1". Therefore, (A2.A1.AO)
= (0,0,1).

Therefore, if you apply a child directly to the encoder without going through a function program that performs a conversion such as j~■→Φ, the correct address output will not be obtained when multiple elements are logical "1". It turns out.

For example, 11. ■If 2 is logic “1”, it is necessary to go through function block X (A2.A1.Ao) −(o, o,
o), resulting in a malfunction. Conventionally, there has been no relatively simple circuit with such a conversion function, and it has been nearly impossible to construct a prioritized address encoder, and even if it was possible, it would be very complicated.

SUMMARY OF THE INVENTION The present invention is a simple circuit of a priority encoder used to send a plurality of signals in a certain order to obtain a binary output. It is intended to provide configuration.

Configuration of the invention Invention id1, signal input terminal i N , signal output terminal Φ
UT1 first clock input terminal C1, second clock input terminal C2, third clock input terminal C3 which is an inverted clock of C2, propagation control input terminal P1, propagation control output terminal P2
, switch circuit s1. s2. s3. s4゜s6. s6,
A logical product circuit (AND) is provided, and the first propagation control output terminal P2 of the circuit element consisting of the above is connected to the propagation control input P1 of the second element, and the propagation control output of the second and subsequent elements is connected. The elements are connected one after another to the propagation control inputs of the elements in the next stage, the propagation control output end of the last element is open, and the element has the same number of input terminals and output terminals as the elements as a whole.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a diagram showing one embodiment thereof.

Pl is the propagation control input, which is the address with higher priority (
In this example, if 1'' is applied as an input signal to even one point in the lower block), and output as an address, I+ 111 will propagate. 0″
will be reset to Once reset, switch S
2, the output holding function continues to hold the reset state at the level set by switch S1. The clock C3 is an inversion of the clock C2, and its appearance is shown in FIG.

The operation of the circuit of FIG. 2 is classified as follows according to the input signal.

(1) P1="1" and node Q is set to 1" by switch S1, but switch S2.S
3. If the reset by S4 has not been performed yet, ΦUT=tN(Q) 10penop2="o" (2) P1="1" and swift S2. S3
．． If the reset by S4 is completed, OUT = ``O'' R2 - ``1''' (3) If P1 = ``O'', ΦUT = ``o'' R2 - ``0'' The above relationship is the input/output truth value The table below shows Table 1
It is.

Furthermore, the state of sequential signal output will be explained in Table 1 according to FIG. Here, the circuit elements are arranged in three columns,
1. Input a potential corresponding to logic "1" to the propagation control input terminal at the head of the circuit element array. / , further connect the propagation control output of the light (π1 ammonium) to the propagation control input of the second element, connect the propagation control output of the second element to the propagation control input of the third element, 3 Let the propagation control output of the element be open. Here, in (iN2, iNl,
iNo ) is the input signal vector, 0UT (OUT2,
0UT1, 0UTo) as the total output signal vector. Fourth
In the illustrated example, the priority is 1No) 1N1) iN2. Now, if iN = (1, 1, 1) and the operation of the example of FIG. 4 is stopped according to the time chart of FIG. 3, the result will be as shown in Table 2.

Table 2 As mentioned above, the circuit in Figure 2 has one signal input iN,
A switch circuit S1 consisting of an N-channel MOS transistor, which has one terminal for propagation control P1, three terminals for clock control C1, C2, C3, one terminal for signal output OUT, and one terminal for propagation control output P2. 521S3. S
4. A switch circuit S1 comprising a switch circuit S6 consisting of an S6P channel MoS transistor and one AND circuit A, and controlled by a clock control human power C1
The output of switch circuit S6. The control input of S6 and the input to the AND circuit are used, and the propagation control human power P1 is input to the switch circuit S.
6 and the other input of AND circuit A, and the input of switch circuit S5 is connected to ground (logical "0" potential),
Its output is common to the output of the switch circuit S6 and is designated as a propagation control output P2. Furthermore, the output of the AND circuit 4 is input to the switch circuit S3 which is controlled by the signal output OUT and (7, this signal output is input to the clock control human power C3), and its output is used to control the switch circuit S4. Connect to the input terminal.The input of the switch circuit S4 is connected to the ground, and the output of the switch circuit S4 is the input of the switch circuit S2 controlled by the clock control human power C2, and the output of the switch circuit S2 is connected to the ground. This is an encoding circuit element consisting of a circuit that shares the output of the switch circuit S1.

Arrange a plurality of such circuit elements in a column, connect the propagation control input terminal of the first element of the encoded circuit element column to vDD (logic "1" potential), and connect the propagation control output of that element to the second column. Priority is given by connecting the propagation control input of the element, connecting the propagation control output of the second and subsequent elements to the propagation control input of the next element one after another, and leaving the propagation control output end of the last element open. You can get a prescription address encoder.

When actually realizing a circuit like the one shown in Figure 2, it is often difficult to configure a logic 14-page product circuit in one stage, and generally negative output logical product (NAND) or negative polarity input logical product (NOR) is used. ) is often used.

FIG. 6d is an example of a circuit using NOR. In this case, since the input logic has negative polarity, the switch circuit S1. S2. S
3. The switch circuit consists of 541S6P channel MoS transistors, 56iN channel MO8) transistors, and a logic inversion circuit is connected to the output of the switch circuit S3.
The output is used as the control input of the switch circuit S. Furthermore, connect vDD to the input of switch circuit S4゜S6 (
Logic "1" potential) is realized.

Figure 5 is another example of a circuit using a NOR. Here, switch circuit s1. s2. s3. s4. s6 to N
The switch circuit S6 is connected to P using a channel MOS transistor.
Channel MO8) Switch circuit S1 composed of transistors
A logic inversion circuit is connected to the output of S5., and its output is connected to the switch circuit S5. Connect to the control input of S6 and the input of NOH.

Furthermore, switch circuit S4. This is realized by connecting the inputs of S5 to ground and vDD, respectively.

When combining multiple prioritized address encoders with the configuration shown in Figure 1, the AND circuit A is made into a three-man type and the third input is further propagated up one level. This can be achieved by using the second propagation control input.

Effects of the Invention As described in detail, the present invention has the following advantages. The L circuit elements are shown in Table 1.
The operation is as shown in the truth table in Table 2, so if you place this circuit element at the part marked X in Figure 1 and connect the propagation control input and output terminals in sequence, the priority level I'' address encoder function can be achieved. I understand that it will be realized.

On the other hand, the overall operating speed of the prioritized address encoder depends on the propagation time of the propagation control signal, and if this is large, the overall operating speed becomes slow. (According to the present invention, however, the propagation control signal has 861 stages of switch circuits for each circuit element, so high-speed operation is possible.

[Brief explanation of drawings]

Figure 1 shows the basics of a prioritized address encoder
O-59595 (5) A schematic configuration diagram showing an example of the body configuration; FIG. 2 is a basic circuit configuration diagram of an encoding circuit element of an embodiment of the present invention having the basic function of a priority birth month address encoder; The figure shows a time chart of the set signal and control clock applied to the encoding circuit element shown in Figure 2, Figure 4 is a diagram explaining how the input signal is output to the preferential membrane, and Figure 5 2A and 2B are circuit configuration diagrams constructed using circuit elements that are easy to realize the encoding circuit elements shown in FIG. 2. C1, C2, C3... Clock control input, sl
, s2. s3゜S4. S5. S6... Switch circuit, A... AND circuit, Pl... Propagation control input, P2... Propagation control output, ■...
...Logic inversion circuit. Name of agent: Patent attorney Toshio Nakao and one other name
1 rA × Y Figure 2 I Figure 3 - Chit Figure 4 C3P3 Figure 5 (C

Claims (2)

[Claims] (1) Signal input, propagation control input, 1st. Second. The first one has a third clock control input, a signal output, and a propagation control output terminal, and is made of a conductive type MO8) transistor. Second.
Third. 4th. A fifth switch circuit includes a sixth switch circuit consisting of a transistor of a different conductivity type and an AND circuit, and the output of the first switch circuit controlled by the first clock and clock control inputs is controlled by the first switch circuit. Fifth. 6th
a control input terminal of the switch circuit and an input of the AND circuit, the propagation control input is an input of the sixth Sui-nochi circuit and another input of the AND circuit, and a potential corresponding to logic "o" is set. is input to the fifth switch circuit, its output is common to the output of the sixth switch circuit and used as a propagation control output, the output of the AND circuit is used as a signal output, and this signal output is used as the signal output of the third switch circuit. to the third switch circuit on the previous page controlled by the clock control input of the fourth switch circuit, the output of which is connected to the control input of the fourth switch circuit, corresponding to the logic rOJ. inputting a potential, inputting the output thereof to the second switch circuit controlled by the second clock control input, and further connecting the output of the second switch circuit in common with the output of the first switch circuit. Arranging a plurality of circuit elements in a row with a configuration of
A potential corresponding to logic "1" is input to the propagation control input terminal at the head of the circuit element array, and furthermore, the propagation control output of the head element is connected to the propagation control input of the second element, and the Connect the propagation control outputs of the elements to the propagation control inputs of the elements in the next stage one after another, leave the propagation control output end of the last element open, and as a whole have the same number of signal input terminals and signal output terminals as the number of elements. An encoding circuit characterized by: (2) First. Second. Third. 4th. Each P-channel MO8) transistor is used as the sixth switch circuit, an N-channel MOS transistor is used as the sixth switch circuit, and a negative polarity input positive polarity output is used as the AND circuit. The output of the first .
Second. inputting a third clock control input at negative pole 4'1;
4th. tr+bow assimilation circuit 3) Fifth switch according to claim 1, characterized in that a potential corresponding to logic "1" is manually applied to the sixth switch circuit to constitute the circuit element. A P-channel MOS transistor is used as the circuit, an N-channel MO3) transistor is used as the sixth switch circuit, a negative polarity input positive polarity output is used as the AND circuit, and the output of the first Swiss-Sochi circuit is used as a logic inversion circuit. Via 5th. A patent claim characterized in that the encoder circuit element is configured by inputting a potential corresponding to a logic "1" to a control input terminal of a sixth switch circuit and an AND circuit, and inputting a potential corresponding to logic "1" to the sixth switch circuit. The encoding circuit according to the first item in the range.