JPH04113469A - Logic simulation processor - Google Patents

Abstract

PURPOSE:To perform simulation with a single processor by arranging an access element between a compression element and a development element and setting the number of input/output terminals of those elements within that of input/ output terminals that can be handled by a single logic simulation processor. CONSTITUTION:The access element 300 is arranged between the compression element 100 and the development element 200. The number of input/output terminals of those elements 100, 200, and 300 are set within the number of input/output terminals that can be handled by the single logic simulation processor. Thereby, a memory element can be allocated on a memory device in the same data structure as that of an ordinary element, which enables the simulation to be performed by the single processor without providing a simulation processor dedicated for memory element.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention provides a first logic system in which simulation target model information in a logic simulation processor exceeds a predetermined number of input/output terminals allocated to memory in the processor. The present invention relates to a logic simulation processor that simulates a simulation target model in which an element and a second logic element having the number of terminals exceeding the number of input/output terminals coexist.

(Prior Art) In an event-driven logic simulation, for example, when simulating a memory element having a memory capacity of a word in 4 bits E34 as shown in FIG.
Attribute data of the memory element itself, state value data, connection destination data, etc.) are converted into normal logic elements (AND, OR, F
/F, etc.) is larger than the amount of information on the simulation target model. Since this has a large number of input/output terminals (26 pins), it is necessary to handle it separately from normal logic elements (for example, 6 inputs and 1 output) and provide a dedicated processor for the memory element. Therefore, dedicated simulation processors are provided for circuits composed of ordinary logic elements and for circuits composed of memory elements, and the overall simulation is executed while information is transmitted between the respective processors.

(Problems to be Solved by the Invention) However, the above-described multiple processor configuration has the following problems. In other words, a dedicated processor is required for each number of input/output terminals that a single processor can handle, which increases the overall amount of hardware, complicates the control between each processor, and increases the amount of communication. This makes logical simulation difficult.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides n bits (n
is a logical simulation processor whose one state value is (a natural number of 2 or more), and the simulation target model information in this logical simulation processor is a logical simulation processor whose upper limit is a predetermined number of input/output terminals allocated to the memory in the processor. In a logic simulation processor that simulates a simulation target model in which one logic element and a second logic element whose number of terminals exceeds the number of input/output terminals,
The logic element inputs m state values of m input terminals (m is less than or equal to n above), associates each of the m state values with 1-bit information, and outputs n as m-bit string information. A compression element that outputs a 1-state value in a bit string, and a 1-state value and an extraction bit position are input, and a 1-state value corresponding to the information extraction bit position of the n-bit string of the input 1 state value is inputted.
An expansion element that outputs a 1-state value from bit information, and a state value of the 1-output terminal of the compression element are considered to be the n input terminals, and the 1-state value of itself is considered to be the n output terminals. and an access element that outputs data, the access element is arranged between the compression element and the expansion element, and the number of input/output terminals of these elements is set to an input/output terminal that can be handled by the single logic simulation processor. This makes it possible to keep it within the number of children.

(Function) According to the present invention, by arranging the expansion element, compression element, and access element configured as described above in combination, the number of input/output terminals that can be handled by the single logic simulation processor can be reduced. Since the number of input/output terminals of a logic element with an excessive number of input/output terminals can be accommodated, both memory elements and normal elements can be allocated on the memory device with the same data structure, and there is no need to provide a simulation processor dedicated to memory elements. Simulation can be performed using a single processor, control and processing during simulation execution can be simplified, and the logical simulation processor itself can be miniaturized.

(Embodiment) For example, a 4-bit f34 word memory element shown in FIG. In order to be able to run the simulation of a normal device (not shown here) with a single processor, the number of input/output terminals is adjusted so that the data structure allocated to the memory of the single processor is the same for both the memory device and the normal device. match. For example, assume that the simulation processor has a data structure in which the maximum data configuration of a normal element can represent a terminal with six inputs and one output.

Therefore, first, we used multiple memory-only elements (100, 200, 30
Prepare 0). and the data structure of the memory-only element (
(number of input/output terminals) within the number of input/output terminals of a normal element. This memory-only element inputs state values of m input terminals, and associates each of the m state values with 1-bit information.
One state value (bits of m or more bits) is used as bit string information.

A compression element (100) that outputs a 1-state value and an extraction bit position is input, and 1-bit information is extracted from the 1-bit information corresponding to the extraction bit position of the bit string of the 1-state value.
An expansion element (200) that outputs a state value and one state value outputted by the compression element are calculated by regarding them as m state values each consisting of one bit, and the one state value of itself is made to correspond to one bit of information. This is an access element (300) that outputs m state values as one state value of an n bit string. These memory-only devices each have the same data structure as normal devices (not shown), so they can be treated in the same way as normal devices during simulation, and the evaluation (arithmetic) processing of each device is performed in the same way as normal devices. Simulation is possible by performing processing corresponding to the element.

In addition, the internal state of the memory element is stored in a memory device (not shown) in the processor (memory status table 2, hereinafter abbreviated as MST), and access to MST is as follows:
This is performed by the arithmetic processing of the access element (300). M
The word length of ST is the number of bits representing one state value, so that it can be expressed as the state value of the data input/output terminal of the access element (300). FIG. 1 is a diagram illustrating a preferred embodiment of the present invention, in which a process for simulating a word memory element in the 4 bits 64 of FIG.
FIG. 2 is a block diagram showing a first embodiment of the internal structure (in which one state value is represented by a bit); One MST with one word length of 4 bits,
4 compression elements (+00) that handle memory addresses, 1 compression element (+00) that handles write data, 1 compression element (+00) that handles control data, 4 expansion elements (200) that handle read data, and access Motoko (300
) Express the circuit using one piece. Memory address and data signals are obtained by converting four state values (one state value consists of 4 bits) into a bit string of 0.1 each, and converting the 16-bit address signal and 4-bit data signal to the access element (30 bits).
0). The chip enable signal (CE) and write enable signal (WE) of the memory element are also input in the same manner. The access element (300) adds the input address and the allocated start address of its own memory on the MST, and reads or writes data. Further, the read data is outputted to the expansion element (200) corresponding to the number of bits as a bit string of 0.1, in which the states corresponding to the number of bits expressing one state value are output.

The expansion elements (200, 201, 202, 203) extract 1 bit, ie, +01, from the extraction bit position “0001” from the beginning specified in the expansion element (200), from the input bit string, and output the 1 state value ( 4 bits) and output.

FIG. 2 shows the internal structure of a processor according to a second embodiment in which memory elements of 64 words each having a word length of 16 bits are simulated. Four access elements (300) are arranged in parallel, one compression element (+00) for memory control signals, five compression elements (+00) for each access element (300), and four expansion elements (200). This is made possible by representing a circuit similar to that shown in Figure 1.

In addition, in these processors, the above-mentioned normal elements having the number of input/output terminals that can perform logic simulation with the processors are omitted from the drawings.

(Effects of the Invention) As explained above, according to the present invention, both memory elements and normal elements are allocated to the memory in the logic emulation processor with the same data structure, and the emulation processor dedicated to the memory elements is Simulation can be performed with a single processor without the need for a processor, the control and processing during simulation execution are simplified, and the logical simulation processor itself can be miniaturized.

[Brief explanation of drawings]

FIG. 1 shows the internal configuration of an embodiment of the present invention, which is a process that can perform logic simulation by replacing a 4-bit/4-word memory element with a plurality of memory-only elements. FIG. 2 shows a second embodiment of the present invention, with a 16-bit 64-bit
Figure 2 shows the circuit configuration of a word memory element using memory-only elements. FIG. 3 shows a memory-only element used in the first and second embodiments of the present invention to represent a circuit of a memory element or the like exceeding the maximum number of input/output terminals. FIG. 4 is a diagram showing the input/output terminal configuration of a conventional memory element having a storage capacity of 4 bits (84 words).

Claims (1)

[Claims] A logic simulation processor whose one state value is n bits (n is a natural number of 2 or more), in which simulation target model information in this logic simulation processor indicates a predetermined number of input/output terminals allocated to memory within the processor. In a logic simulation processor that simulates a simulation target model in which a first logic element with an upper limit and a second logic element with a number of terminals exceeding the number of input/output terminals are mixed, the second logic The element receives m state values from m input terminals (m is less than or equal to n above), associates each of the m state values with 1-bit information, and converts the m-bit string information into an n-bit string. a compression element that outputs a 1-state value;
an expansion element into which a 1-state value and a take-out bit position are input, and outputs a 1-state value from 1-bit information corresponding to the take-out bit position of information in the n-bit string of the input 1-state value; and 1 output of the compression element. an access element that calculates a state value of a terminal by regarding it as the n input terminals, and outputs one state value of itself by regarding it as the n output terminals,
The access element is arranged between the compression element and the expansion element, and the number of input/output terminals of these elements is within the number of input/output terminals that can be handled by the single logic simulation processor. A logical simulation processor.