JPS6236575A - Transition analysis model system - Google Patents
Transition analysis model systemInfo
- Publication number
- JPS6236575A JPS6236575A JP60177213A JP17721385A JPS6236575A JP S6236575 A JPS6236575 A JP S6236575A JP 60177213 A JP60177213 A JP 60177213A JP 17721385 A JP17721385 A JP 17721385A JP S6236575 A JPS6236575 A JP S6236575A
- Authority
- JP
- Japan
- Prior art keywords
- input
- transient analysis
- logic circuit
- input terminal
- analyzed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 方式に関する。[Detailed description of the invention] [Industrial application field] Regarding the method.
従来の過渡解析モデル方式は、被過渡解析論理回路につ
いてのみモデル化していた。Conventional transient analysis modeling methods model only the logic circuit subjected to transient analysis.
このような従来の技術としては、「超Ｌ Ｓ Ｉ ＣＡ
Ｄの基礎、第３章電子回路のＣＡＤＪ （オーム社１９
８４年１２月）がある。As such conventional technology, "Ultra LSI CA
Fundamentals of D, Chapter 3 CADJ of electronic circuits (Ohmsha 19
December 1984).
しかしながら、このような上述した従来の過渡解析モデ
ル方式は、被過渡解析論理回路についてのみ行っている
ので、被過渡解析論理回路への入力波形は理想的なもの
になシ（シかし、現実的には上記論理回路の前には別の
論理回路があり、理想的な波形が伝達することはありえ
ない）、被過渡解析論理回路の過渡解析結果が現実に合
わないという欠点がある。However, since the conventional transient analysis model method described above is performed only on the logic circuit subjected to transient analysis, the input waveform to the logic circuit subjected to transient analysis may not be ideal (although it may not be possible in reality). In other words, there is another logic circuit in front of the above logic circuit, so it is impossible for an ideal waveform to be transmitted), and there is a drawback that the transient analysis results of the logic circuit subjected to transient analysis do not match reality.
本発明の過渡解析論理回路と、この被過渡解析論理回路
の前に入力波形生成回路を有に構成される。The transient analysis logic circuit of the present invention and an input waveform generation circuit are arranged in front of the transient analysis logic circuit.
次に、本発明の実施例について、図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.
第１図に示す過渡解析モデル方式は、被過渡解析論理回
路１の入力端子５と自由に変えることができる抵抗６、
容量７とを持つ入力波形生成回路２の出力端子４とが接
続されている。The transient analysis model method shown in FIG.
The output terminal 4 of the input waveform generation circuit 2 having a capacitor 7 is connected thereto.
これにより、入力波形生成回路２の入力端子３に電圧波
形を入力すると、それが信号伝播され、よシ現実的な電
圧波形となって被過渡解析論理回１の入力端子５に入力
させることができる。As a result, when a voltage waveform is input to the input terminal 3 of the input waveform generation circuit 2, it is signal-propagated, becomes a more realistic voltage waveform, and can be input to the input terminal 5 of the transient analysis logic circuit 1. can.
被過渡解析論理回路１に入力端子５が複数ある場合には
、それぞれに入力波形生成回路２をつける。If the transient analysis logic circuit 1 has a plurality of input terminals 5, an input waveform generation circuit 2 is attached to each of them.
また、入力波形生成回路２としては一般的な論理回路を
用いてもよい。Further, as the input waveform generation circuit 2, a general logic circuit may be used.
本発明の過渡解析モデル方式は、被過渡解析論理回路の
前に入力波形生成回路をつけることによシ被過渡解析論
理回路の入力端子に与える波形をよシ現爽のものにする
ことにより、被過渡解析論理回路の過渡解析をよシ正確
に解析することができるという効果がある。The transient analysis model method of the present invention provides a more modern waveform to be applied to the input terminal of the transient analysis logic circuit by adding an input waveform generation circuit in front of the transient analysis logic circuit. This has the effect that the transient analysis of the logic circuit to be subjected to transient analysis can be performed more accurately.
第１図は本発明の一実施例を示すブロック図である。
１・・・・・・被過渡解析論理回路、２−・・・・・入
力波形生成回路、３・・・・・・入力端子、４・・・・
・・出力端子、５・・・−・・入力端子、６・・・・・
・抵抗、７・・・・・・容量。FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Transient analysis logic circuit, 2-... Input waveform generation circuit, 3... Input terminal, 4...
...Output terminal, 5...--Input terminal, 6...
・Resistance, 7... Capacity.
Claims (1)
設けられた入力波形生成回路とを含むことを特徴とする
過渡解析モデル方式。A transient analysis model method comprising a transient analysis logic circuit and an input waveform generation circuit provided before the transient analysis logic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60177213A JPS6236575A (en) | 1985-08-12 | 1985-08-12 | Transition analysis model system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60177213A JPS6236575A (en) | 1985-08-12 | 1985-08-12 | Transition analysis model system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6236575A true JPS6236575A (en) | 1987-02-17 |
Family
ID=16027139
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60177213A Pending JPS6236575A (en) | 1985-08-12 | 1985-08-12 | Transition analysis model system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6236575A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6922795B2 (en) | 1998-03-31 | 2005-07-26 | Seiko Epson Corporation | Microcomputer, electronic equipment, and debugging system |
-
1985
- 1985-08-12 JP JP60177213A patent/JPS6236575A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6922795B2 (en) | 1998-03-31 | 2005-07-26 | Seiko Epson Corporation | Microcomputer, electronic equipment, and debugging system |
| US7065678B2 (en) | 1998-03-31 | 2006-06-20 | Seiko Epson Corporation | Microcomputer, electronic equipment, and debugging system |
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