JPH04135281A - Logic simulation device - Google Patents

Abstract

PURPOSE:To shorten the processing time and to improve the precision by performing the operation with input/output relations of a resistance element as the function of the shortest operation time and simulating the delay due to wiring also. CONSTITUTION:A logic circuit is simulated by a resistance element 31 where an L-tye circuit of CR is substituted with a four-terminal circuit and a threshold element 71 expressing the logic gate, and the operation is performed with input/ output relations of the resistance element 31 as the function of a minimum operation time DELTAt. Consequently, the delay due to wiring is simulated by the operation of the resistance element 31, and this operation and the logic conversion of the threshold element 71 are combined to simulate the whole of the logic circuit including the delay. Thus, it is unnecessary to calculate the wiring delay and assign the delay of the logic gate before logic simulation, and the processing time is shortened and the precision is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a logic simulation device for performing logic simulation of a logic circuit.

〔overview〕

The present invention is a logic simulation device that performs logic simulation of a logic circuit, in which the logic circuit is simulated using a resistance element in which a CROL type circuit is replaced with a four-terminal circuit, and a threshold element representing a logic gate, and a This method aims to shorten processing time and improve accuracy by performing calculations related to the human output of the resistance element as a function of calculation time, and by making it possible to simulate delays caused by wiring.

[Conventional technology]

Logic simulation is used in designing logic circuits. This is an attempt to verify the correctness of the operation of a logic circuit using a computer.

The first thing that is verified in logic simulation is the correctness of the logic operation, but recently it has also become important to verify the timing, such as whether the time relationships between the signals in each part are such that the circuit operates correctly. ing.

A typical method used to verify this timing is to allocate a delay time to each of the logic gates that make up the logic circuit, and to transmit a change in the output of one gate to the next gate after that gate's delay time. (for example,
(Refer to "rVLSI Design ■Logic and Testing" by Yukizo Kishita et al., published by Iwanami Shoten, p. 200).

According to this technique, the delay caused by wiring from the output of one gate to the input of the next gate is calculated in advance and assigned as the gate delay. For example, in the circuit diagram of FIG. 7, the delay caused by the wiring from the output terminal 24 of the logic gate 21 to the input terminals 25 and 26 of the logic gates 22 and 23 is calculated in advance, and is not included in the delay time of the logic gate 21. It will be done.

[Problem to be solved by the invention]

According to the logic simulation method used by the conventional logic simulation apparatus described above, in order to take wiring delays into account, it is necessary to calculate the wiring delays and assign them to logic gates prior to the logic simulation. In particular, when attempting to take into account the resistance of wiring when calculating wiring delay in order to cope with the increasing resistance of wiring due to the miniaturization of integrated circuits in recent years, calculating wiring delay becomes difficult and difficult to calculate. This has the disadvantage that it requires a huge amount of time or else the accuracy is significantly degraded.

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic simulation device that can simulate logic circuits including wiring delays in a short time and with high accuracy by eliminating the above-mentioned drawbacks.

[Means to solve the problem]

The present invention provides a logic simulation apparatus equipped with means for performing logic simulation of a logic circuit, in which the logic circuit is connected to a wiring element having an input terminal including at least one main input terminal and an output terminal including at least one main output terminal. and a threshold element having at least one input terminal and an output terminal; and the wiring element is configured to simulate a threshold value element having at least one input terminal and an output terminal; a wiring element calculation means that performs an operation when an operation is performed on another wiring element connected to the terminal; When a calculation is completed in a set of the wiring element and the threshold element that are connected to each other, a threshold element calculation means that sometimes performs the calculation, and at least one of the set of the wiring element and the threshold element are The present invention is characterized by a calculation control means that sets the calculation of the wiring element that was calculated first in the set to be calculated at the next calculation time when the value of the output of one element changes.

Further, in the present invention, it is preferable that the wiring element is based on a circuit in which one resistor and one capacitor are connected in an L-shape to a four-terminal circuit.

Further, in the present invention, it is preferable that the wiring element calculation means is a means for calculating the relationship between the input and output of the wiring element as a function of a minimum unit of calculation time Δt.

[Effect]

A simulation is performed using a resistance element in which the logic circuit is replaced with a CROL type circuit type circuit and a threshold element representing a logic gate, and the input/output relationship of the resistance element is calculated as a function of the minimum calculation time Δt.

Therefore, the delay caused by the wiring is simulated by the calculation of the resistance element, and by combining this with the logic conversion by the threshold element, it is possible to simulate the entire logic circuit including the delay.

This eliminates the need to calculate wiring delays and allocate delays to logic gates prior to logic simulation, making it possible to shorten processing time and improve accuracy.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

This embodiment is a logic simulation apparatus equipped with means for performing logic simulation of a logic circuit, which is a feature of the present invention. simulation means 11 for simulating a wiring element having an output terminal and a threshold element having at least one input terminal and an output terminal, said wiring element having a logic connected to its main input terminal; Wiring element calculation means 12 that executes an operation when the output of the gate element changes or when an operation is executed in another wiring element connected to the main input terminal, and the threshold element has an input terminal thereof. a threshold element calculation means 13 that executes the calculation when the calculation is performed in the wiring element connected to the wiring element; and a threshold element calculating means 13 that executes the calculation when the calculation is performed in the wiring element connected to the Sometimes, when the value of the output of at least one element in the set changes in the calculation, calculation control is performed to schedule the calculation of the wiring element that was calculated first in the set to the next calculation time. means 14.

Note that here, the simulation means 11, the wiring element calculation means 12, the threshold element calculation means 13, and the calculation control means 14 are included in the processor (CPU) 10.

Further, 1 is logic circuit data and 2 is output data, which are respectively stored in the auxiliary storage device.

Next, Figure 2, Figure 3 (a) and Figure 4 (a)
The operation of this embodiment will be described with reference to FIGS.

Here, Fig. 2 is a flowchart showing the operation of Fig. 1, and Fig. 3 (
a) and (b) are diagrams showing wiring elements, FIGS. 4(a) and 4) are diagrams showing simulation example (1), FIG. a) and (b)
) is a diagram showing simulation example (2).

The present invention is to perform a simulation by dividing wiring into unit sections and replacing the unit sections with wiring elements.

For example, a wiring consisting of a capacitor and a resistor can be accurately represented as a connection of an L-shaped circuit consisting of one resistor R31 and one capacitor C32 shown in FIG. 3(a).

This L-shaped circuit is connected to a wiring element 41 as shown in FIG. 3(b).
Replace with Here, the main input terminal 42 corresponds to the input voltage Vr)I of the L-type circuit, and the main output terminal 44 corresponds to the output voltage Vr) of the L-type circuit. Corresponds to Ua. Therefore, connecting an L-shaped circuit corresponds to connecting the main output terminal of one wiring element to the main input terminal of the next wiring element.

Further, for convenience of calculation, it is generally necessary to provide another input terminal 43 and another blade terminal 45.

The operation of wiring elements is defined to represent the operation of an L-type circuit. Assuming that the value of VIH at calculation time t is VIN(t) and the minimum unit of calculation time is Δt, the following definition is possible as an example.

Jry(t+Δt)'=(Vout(t+Δt)−■
.ゎy(t))/R, (1) Iout(t+Δt)=(v+x(t+Δt)−■.

t+r(t)) Δt/C (2) In other words, I is connected to the other input terminal 43. UT, and the other blade terminal 45 has 1
111 corresponds.

In this case, the connection of L-shaped circuits as shown in FIG. 4(a) can be expressed by the connection of wiring elements shown in FIG.

4), the main input terminal 63 of the wiring element 61 is connected to the main output terminal of the previous stage, and the other input terminal 65 is connected to the other blade terminal 70 of the wiring element 62 of the next stage. Further, the main input terminal 64 of the wiring element 62 is connected to the main output terminal 67 of the wiring element 61, and the other input terminal 66 is connected to the other blade terminal of the next stage.

A threshold element 71 shown in FIG. 5 is always connected between the main output terminal of the wiring element and the input terminal of the logic gate. It outputs a logical value at output terminal 73 according to the value on input terminal 72. - For example, in the case of positive logic, perform the following calculation according to predetermined threshold values VL and VB (VH≧vL).

When VTN≦vL, V(H7-Logic “0” V L
When < V 1w < V B, VOLIT = logic "
X”V I II ≧V M (When D Vout=
Logic "1" Next, we will explain how the simulation of logic circuit data 1 having the wiring represented by the connection of the wiring elements shown in Figs. 3 and 5 and the threshold element shown in Fig. This will be explained with reference to the flowchart in Figure 2.

In FIG. 2, first, in step S1, logic circuit data 1 is
is simulated using the wiring element and threshold element. Then, if the output logic value of the logic gate input to the wiring element changes at a certain time t, step S2
The wiring element is calculated using . Next, it is checked in step S3 whether the output light of the wiring element is a wiring element, and if it is a wiring element, the process returns to step S2 and calculations are performed. This is repeated until the threshold element is reached.

When the threshold element is reached, the calculation of the threshold element is executed in step S4, and the output of the threshold element is checked in step S5 to see if it has changed. Register an event.

After that, in step S7, it is checked whether or not there is a value change among the outputs of the wiring elements and threshold elements, and if there is any, the calculation of the wiring element calculated first is scheduled at the next calculation time t+Δt. , returns to processing of other events scheduled at this time t. If I don't have one, I won't do anything.

As described above, the behavior of wiring can be handled in logic simulation.

FIGS. 6(a) and 6(5) are other simulation examples according to this embodiment. FIG. 6(a) shows a case where there is a wiring branch. In such a case, a wiring element 91 having two other input terminals 94 and 95 is used in the L-shaped space consisting of the resistor 81 and the capacitor 84 in FIGS.

Other input terminals 94 and 95 are a wiring element 92 corresponding to an L-shaped diagram consisting of a resistor 82 and a capacitor 85, and a wiring element 93 corresponding to an L-shaped diagram consisting of a resistor 83 and a capacitor 86, respectively. 97. The calculation for the wiring element 91 in this case is I in the above equation (2). UT is replaced with the sum of the values of other input terminals 94 and 95 (in this case I3+I4).

The simulation method when there is a branch is basically the second
Although it is the same as the figure, it becomes necessary to select only one of the branches in step S3, and the one that is not selected is separately recorded as an unprocessed element. And step S
After the calculation of the threshold value elements is completed in step S4, it is checked whether there are any unprocessed elements remaining, and if so, the process returns to step S2 and the calculation is restarted from that element.

〔Effect of the invention〕

As explained above, the present invention makes it possible to simulate wiring delays during logic simulation, and eliminates the need for calculating wiring delays and assigning them to logic gates prior to logic simulation, which was required in the past. , the overall processing time can be reduced, and since no approximation calculations are required, highly accurate results can be obtained even for complex wiring.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a flowchart showing the operation. FIGS. 3(a) and 3(5) are diagrams showing wiring elements. Figures 4(a) and 3) show simulation example (1). Figure 5 shows a threshold element. Figure 6 (a) and 6) show simulation example (2). figure. FIG. 7 is a circuit diagram showing a conventional logic circuit. 1...Logic circuit data, 2...Output data, 10.
... Processor (CPU), 11... Simulation means, 12... Wiring element calculation means, 13... Threshold element calculation means, 14... Calculation control means, 21.2
2.23...Logic gate, 31.51.52.81.
82.83...Resistance, 32.53.54.84.85
．． 86...Capacity, 41.61.62.91.92.9
3... Wiring element, 71... Threshold element, 31-S
8...Step.

Claims (1)

[Scope of Claims] 1. A logic simulation device equipped with means for performing logic simulation of a logic circuit, in which the logic circuit is connected to an input terminal including at least one main input terminal and an output terminal including at least one main output terminal. and a threshold element having at least one input terminal and an output terminal; a simulation means for simulating a wiring element having a threshold value element having at least one input terminal and an output terminal; wiring element calculation means that executes an operation when the calculation is performed at the time or when the calculation is performed in another wiring element connected to the main input terminal; a threshold element calculation means for performing an operation when an operation is executed; and calculation control means for setting the calculation of the wiring element that was calculated first in the set to be calculated at the next calculation time when the value of the output of at least one element in the set changes. A logic simulation device characterized by: 2. The logic simulation apparatus according to claim 1, wherein the wiring element is basically a four-terminal circuit replacing a circuit in which one resistor and one capacitor are connected in an L-shape. 3. The logic simulation apparatus according to claim 1 or 2, wherein the wiring element calculation means is means for calculating the relationship between the input and output of the wiring element as a function of a minimum unit of calculation time Δt.