JPS61280116A - Phase comparator - Google Patents

Abstract

PURPOSE:To decrease a test time and to simplify a test method by providing a state setting terminal to which each state setting signal is inputted to each of the 1st and 2nd flip-flop circuits in pairs. CONSTITUTION:A state setting signal (j) is brought into 'H' level to compare the phase of comparison object signals (a, b). Even when the state setting signal (j) is brought into 'H' level in this case, the circuit state of the phase comparison circuit is unchanged 3-input NAND gates 3B, 4B of the 1st and 2nd flip-flop circuits 3, 4 act like 2-input NAND gates because the signal (j) is at the 'H' level. When the phase of the comparison object signal (a) is led more than that of the signal (b), an H level signal comes from a tri-state circuit 8 in response to the phase difference between both the comparison object signals, and when the phase of the signal (b) is led more than that of the signal (a), an L level signal is given from the tri-state circuit 8 corresponding to the phase difference between both the comparison object signals.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase comparator circuit, which is a type of logic circuit.

[Conventional technology]

Figure 3 shows a conventional phase comparator circuit of this kind in which the falling edge of the signal compares 9 hD. 2 input NA
ND game), (21 is the second 2-input WAND gate where the second comparison target signal is input to the 1 input terminal, (31U is the set terminal (3a) to which the set signal C is input, and the reset signal g is input. The reset terminal (3b) and the output terminal (
3C), and the set terminal (3a) becomes the first reset-priority flip-flop terminal (3b) connected to the output terminal of the first two-input NAND gate (11);
It consists of a 2-input NAND gate (C, 5B) whose output end is connected to the A2 input end of the 2-input NAND gate (5A). (4
) has a set terminal (4a) to which the set signal d is input, a reset terminal (4b) to which the reset signal g is input, and an output terminal (4C), and the set terminal (4a) is connected to the second
2 connected 2-input NAND game) (4B). (5) C The above first two inputs N
Signal 0 from the AND gate (1), signal e from the first flip-flop circuit (3), and second two inputs N
This is a 4-input NAND gate into which the signal d from the AND gate (2) and the signal f from the second flip-flop circuit (4) are input, and the output signal is sent to the first and second clip-flop circuits (3). ) (This also serves as the reset signal g of 41. (6) is the signal C from the first 2-input NAND gate (11), the signal e from the first flip-flop circuit (3), and the 4 The first 3-input NAND gate is input to the signal from the input NAND gate (5), and its output signal is also input to the 2 input terminals of the first 2-input NAND gate (1). It is something.

(7) is the signal d from the second two-input NAND gate (2), the signal from the second flip-flop circuit (4), and the signal g from the four-person car AND gate (5).
and a second 3-input NAND gate.

The output signal 1 is the second 2-input NAND gate (2
) is also input to the 2 input terminals. (8) are these first and second 3-input NAND gates (6) (
7) is a tri-state circuit into which 1 is input, and the first and second 3-input NAND game) (61 (7)
When the signals from 1 to 1 are both at K ``E'' level, it becomes a high impedance state, and when the signal 1 is at ``L'' level and the signal 1 is at ``H'' level, it goes to ``H#H#'' level, and the signal -H
``1/Helte tjt i When the level is 11', @Rebel is output.

Next, the operation of the phase comparator circuit configured in this manner will be explained. First, as an initial state, a 4-input NAND gate (5
) from the first and second flip-flop circuits (31 (41 is reset and the first
and the second flip-flop circuit (31(4)), the signals e and f from the first and second three inputs N
It is assumed that the signals 1 from the AND gates (6) and (7) are at the ``Hm level.Furthermore, after the state of this phase comparison circuit is determined, the first and second comparison target signals Assume that both a and b change to the 1L# level or @H'' level, resulting in the state 1 shown in the fourth garden. In such a state, both the first and second comparison target signals a and b are @H level, so the first and second two-input NAN
The signals C#d from the D gate (11T2) are both @L'' level, and the first and second 7-rip-frog circuits (3
1 (41 is set, and the signals e and f from this 1 are “H”
” level.Then, the comparison target signal a falls, and the output signal C of the first 2-input NIJD gate (1)
When becomes “H” level, @1 3-input NAND gate (
Since all inputs of 6) are at 1H" level, their output signals are at 1H" level.On the other hand,

This is because the signals to be compared are up to ``H'' level 1.

Signal 1 from the second 3-input WAND gate (7) is 'H
” level. Therefore, the tri-state circuit (
8)'s output becomes @H" level. Next, when the comparison target signal falls, the second 2-input WAND gate (2)
The output signal d of the 4-input NARD gate (51O4 inputs, that is, the signals (C) (e) (f) (
d) are all at the "■" level, their output signals g are no longer at the 1Lm level, the first and second flip-flop circuits (3) and (4) are reset, and their output signals e,
f also goes to -" level. As a result, the signals from the first and second 3-input NAND gates (6) (7) and i both go to "H" level, so the tri-state circuit (8)
still changes to an impedance state. Therefore, when the comparison target signal a is ahead of the comparison target signal, an "H" level signal is output from the tristate circuit (8) corresponding to the phase difference between the target signals a and b. be.

Furthermore, as shown in state 2 in FIG. 4, even if comparison target signal a rises before comparison target signal A falls, the signal from the 4-input NAND gate (5) Since the signal does not reach the 1Lm level until the signal falls, the tristate circuit (8) outputs a signal at the 1H'' level in response to the phase difference between the comparison target signals a and b, as described above.

On the other hand, if the comparison target signal is ahead of the comparison target signal a, as can be seen from the above description.

When the comparison target signal falls, the signal 1 from the second 3-input NAND gate (7) goes to 1L" level, and the signal from the first 3-input NAND gate (6) goes to @H# level. Therefore, the tri-state circuit (8) outputs a @L" level signal, and then when the comparison target signal a falls, the signal g from the 4-input NAND gate (5) becomes "
The first and second flip-flop circuits (31 (41) are reset and their output signals e,
f is @L” level.

The signals from the first and second 3-input NAND gates (61 (7)) are both at "H" level, and the tri-state circuit (8) changes to a high impedance state. In other words, The tri-state circuit (8) outputs an L'L' level in response to the phase difference between the comparison target signals S and a.

[Problem that the invention seeks to solve]

However, in a phase comparator circuit configured in this way, the state of the circuit is not determined in the initial state such as when the N source is turned on. The expected pattern of the signal from the tri-state circuit (8) cannot be known until after the circuit state is determined. the result.

When testing this phase comparator circuit, there are problems in that the test time is long and the test method is complicated.

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to obtain a phase comparator circuit that can easily determine the circuit state, shorten test time, and simplify test methods. .

[Means for solving problems]

In the phase comparison circuit according to the present invention, each of a pair of first and second flip-flop circuits is provided with a state setting terminal to which a state setting signal is input.

Further, a phase comparator circuit according to another aspect of the present invention includes a signal from a four-input NAND gate to which signals from a pair of first and second flip-flop circuits and a pair of set signals are input, and a state setting signal. 2-input NAND
A gate is provided, and the output terminal of this two-input NAND gate is connected to the reset terminals of the first and second flip-flop circuits.

[Effect]

In this invention, a pair of first terminals each having a state setting terminal are provided.
When a state setting signal is input to the second flip-flop circuit, the circuit states of both flip-flop circuits are determined, and the circuit state of the first phase comparator circuit is determined.

Further, in another invention of this invention, a two-input NAND
When a state setting signal is input to the gate, these two input NA
A reset signal is inputted from the ND gate to the pair of gt and the second flip-flop circuit, and the circuit states of both flip-flop circuits are determined, and the circuit state of the phase comparison circuit is determined.

〔Example〕

An embodiment of the present invention will be described below based on FIG. 1. In FIG. 1, (3) a set terminal (3a) to which a Hasset signal C is input; and a reset terminal (3b) to which a reset signal g is input. and a state setting terminal (3d) to which a state setting signal j is input, and an output terminal (3C), and a set terminal (3a) is a first two-input NAND gate input NAND.
It is connected to the output terminal of the gate (3A), the second input terminal becomes the reset terminal (3b), the third input terminal becomes the state setting terminal (3d), and the output terminal is the above two-input NAllID.
3-input NAN connected to @2 input terminal of gate (3A)
It is composed of a D gate (3B). (
4) is a set terminal (4a) to which a set signal d is input, a reset terminal (4b) to which a reset signal g is input, a state setting terminal (4d) to which a state setting signal j is input, and an output terminal (4C). and the set terminal (4a) is the second
A second flip-flop circuit with reset priority is connected to the output terminal of the input NAND gate (2), the first input terminal serves as the set terminal (4a), and the output terminal serves as the output terminal (
4C), the first input terminal is connected to the output terminal of the 2-input NAND gate (4A), the second input terminal becomes the reset terminal (4b), and the third input terminal is a state setting terminal (4d), and a 3-input NAND gate (4B) whose output terminal is connected to the second input terminal of the 2-input NAND gate (4A).

Next, the operation of the phase comparator circuit configured in this manner will be explained. First, when the power is turned on, the status setting signal j is set to 1L.
” level and input. Then, the first and second flip-flop circuits + 3) (4) has reset priority, so the first and second two-input NAND gates (1)
(Regardless of the levels of signals c and d from 21,
The first and second flip-flop circuits (31 (signals e and f from 41 are @L'' level).

First and second 3-input NANII gates (6) (7)
The signal h#i from is at one level, and the tristate circuit (8) is in a high impedance state. here.

Each of the signals RI and i is a flip-flop consisting of a first 2-input NAND gate (l) and a first 3-input NAND gate (6), a second 2-input NAND gate (2), and a second 3-input NAND gate (2). 11 The circuit state of the phase comparison path is determined. That means that. After that, the state setting signal j is set to 1H#
level, and the phases of comparison target signal a and comparison target signal S are compared. At this time, the state setting signal j is
# level also does not change the circuit state of the phase comparison circuit, and the state setting signal j of the first and second flip-flop circuits (3) (41, 3-input NAND gates (1) (4B) is 'H'). level, so it operates in the same way as a two-input NAND gate.Therefore, it operates in the same way as shown in Figure 3 above, and if the comparison target signal a is ahead of the comparison target signal, both comparison targets Corresponding to the phase difference of the signals, a 1■” level signal appears from the tristate circuit (8),
If the comparison target signal is ahead of the comparison target signal a, a -level signal will appear from the tristate circuit (8) corresponding to the phase difference between the two comparison target signals. be.

Therefore, the phase comparator circuit configured in this way is as follows.

First, the state of the circuit 1 is determined by the simple method of inputting the state setting signal j at the ``L#L# level.
Tri-state circuit (8) for comparison target signals a and b
The output from the test can be determined reliably, and the test time can be shortened.

Fig. 2 shows another embodiment of the present invention. In Fig. 91, (9) is a 2-input terminal to which the signal from the 4-input NAND gate (5) is input, and the state setting signal j is input. It is a NAND gate, and the output terminal is connected to the first and second flip-flop circuits (31 (reset terminal (3a) of 41).
(, b) is connected to n.

Even in a phase comparator circuit configured in this way.

If the status setting signal j is set to "L" level and input when the power is turned on, the signal vg from the AND gate (9) becomes @L"
Level Nijima first and second flip-flop circuits (3
1 (41), the circuit state is determined in the same way as shown in FIG.
) corresponds to the signal from the 4-input NAND gate (5), so the phase comparison of comparison target signals a and b also operates in the same manner as shown in FIG.

〔Effect of the invention〕

As described above, the present invention allows the circuit state to be determined by the state setting signal.

This has the effect of shortening the test time and simplifying the test method.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a diagram showing another embodiment of the present invention, FIG. 3 is a block diagram showing a conventional phase comparison circuit, and FIG. 4 is a diagram showing signals of each part. In the figure, (3) is the first flip-flop circuit. (3a) (3b) (3c) (M) are its set terminals, 7) terminals, output terminals and status setting terminals, (4)
is the second flip-flop circuit, (4a) (4b)
(4c) and (4d) are the set terminal, reset terminal, output terminal, and state setting terminal. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (4)

[Claims] (1) A first flip-flop circuit having a set terminal to which a set signal is input, a reset terminal to which a reset signal is input, a state setting terminal to which a state setting signal is input, and an output terminal; It has a set terminal to which it is input, a reset terminal to which a reset signal is input, a state setting terminal to which a state setting signal is input, and an output terminal, and the reset terminal and the state setting terminal are used to reset the first flip-flop circuit. A phase comparison circuit including a second flip-flop circuit connected to a terminal and a state setting terminal, respectively. (2) Each of the first and second flip-flop circuits includes a two-input NAND gate whose first input terminal serves as a set terminal and whose output terminal serves as an output terminal, and a two-input NAND gate whose first input terminal serves as a set terminal and whose output terminal serves as an output terminal.
A 3-input NAND gate connected to the output terminal of the input NAND gate, the second input terminal serves as a reset terminal, the third input terminal serves as a state setting terminal, and the output terminal is connected to the second input terminal of the 2-input NAND gate. A phase comparator circuit according to claim 1, characterized in that it consists of: (3) A first flip-flop circuit having a set terminal, a reset terminal, and an output terminal into which the first set signal is input, and a set terminal, a reset terminal, and an output terminal into which the second set signal is input. a second flip-flop circuit, a 4-input NAND gate to which the signals from the first and second flip-flop circuits and the first and second set signals are input; signals and state settings from the 4-input NAND gate; A phase comparator circuit comprising a two-input NAND gate, into which a signal is input, and whose output terminal is connected to the reset terminals of the first and second flip-flop circuits. (4) The first and second flip-flop circuits each include a two-input NAND gate A whose first input terminal serves as a set terminal and whose output terminal serves as an output terminal, and a two-input NAND gate A whose first input terminal serves as a set terminal and whose output terminal serves as an output terminal.
It is connected to the output terminal of the input NAND gate A, the second input terminal becomes the reset terminal, and the two-input NAND gate B is connected to the second input terminal of the two-input NAND gate A. A phase comparator circuit according to claim 3, characterized in that: