JPS62132182A - Large integrated circuit with test circuit - Google Patents

Abstract

PURPOSE:To enable testing of a circuit block to be tested individually, by providing a test circuit into a large integrated circuit in which a selector function is provided to independently separate a plurality of testing routes. CONSTITUTION:Tristate buffers 31 and 32 and 41-44 wired ORed to one another are provided at a digital signal output section of circuit blocks 21-26 and at an output section of a testing input data of a testing circuit 10, which is provided with a test mode selection external terminal 2 to input a series test mode selection information and a decoder circuit 11 to decode series test mode selection information. Then, an output signal of the circuit 11 is outputted as control signal for tristate buffers 31 and 32 and 41-44. This functions as selector and a selector circuit 12 selects a digital output signal alone of a circuit block to be tested among from that inputted to the circuit 10 from the circuit blocks 21-26 and outputs it to a testing output data terminal. This enables the independent separation of a plurality of test routes to enable testing of circuit blocks to be tested individually.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a large-scale integrated circuit, and particularly to a large-scale integrated circuit with a built-in test circuit for simplifying testing.

[Prior art]

In recent years, with advances in large-scale integrated circuit (hereinafter referred to as LSI) technology, various LSIs have been developed. Some of these include large scale, complex circuit configurations, and mixed analog and digital. When testing these LSIs, if an attempt is made to test all the circuits, the test itself becomes very difficult because the test method becomes complicated and the test time becomes long. Therefore, in order to simplify the evaluation and inspection of these LSIs, LSIs have been known that have a test function inside the LSI. In such LSI testing, all circuits are tested in one test using, for example, the scan path method.

[Problem that the invention seeks to solve]

As mentioned above, conventional testing methods, such as the scan path method, test all circuits with one-way tests, so the LS
If the scale of I is large, the test scale will also be large, the test time will be long, and it will be extremely difficult to create input/output information for the test, making the test itself difficult.

Furthermore, in LSIs that have both analog and digital components, there are many signals that are not directly output to the external terminals of the LSI, such as digital signals for controlling the analog section generated by the digital section and digital signals generated by the analog section. Therefore, there are problems in that there are some circuit blocks that cannot be directly tested.

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, an object of the present invention is to provide a large-scale integrated circuit with a test circuit in which a plurality of test circuits are separated and made independent so that circuit blocks under test can be tested individually. .

[Means for solving problems]

In order to achieve the above object, the present invention provides a large-scale integrated circuit having a plurality of circuit blocks and a test circuit for testing the circuit blocks, in which a digital signal output section in the circuit block and a test input of the test circuit are provided. A tri-state buffer is provided in the data output section, the tri-state buffer is connected with a wire-OR, and the test circuit has an external terminal for selecting a test mode, and serial test mode selection information is transmitted from the external terminal for selecting the test mode to the test circuit. a decoder circuit having a function of inputting the serial test mode selection information into a circuit and decoding the serial test mode selection information in the test circuit;
The output signal of the decoder circuit is transferred to the tristate buffer 1.
Output as a control signal of the tristate buffer? is provided with a function as a selector, the digital output signal of the circuit block is input to the test circuit, and the test circuit is provided with a function of selecting only the digital output signal of the circuit block under test. The test paths are separated and made independent so that the circuit blocks under test can be tested individually.

〔Example〕

Next, the present invention will be explained by way of example with reference to the drawings.

The drawing is a circuit diagram of a large-scale integrated circuit with a test circuit according to an embodiment of the present invention.

In this embodiment, 1 is a line that separates the inside and outside of the LSI, and the right side of the line is the inside of the LSI.

2 is an external terminal for selecting a test mode. 10 is a test circuit, 11 is a decoder circuit that decodes a test mode selection signal input from the external terminal 2, and 12 is a selector circuit. 21-26 are circuit blocks, 31, 32. 41-
44 is a tristate buffer, and 51 and 52 are inverters.

61 and 62 are test input data terminals, and 63 is a test output data terminal.

In the above configuration example, a case where the circuit block 23 is tested will be described. First, during normal operation, decoder circuit 1
All output signals from 1 are at “L It level,”
The tristate buffers 31 and 32 are in the OFF state, and the tristate buffers 41 to 44 are in the ON state. Therefore, it is equivalent to not connecting the test circuit 10 to each circuit block.

When testing the circuit block 23, test mode selection information corresponding to the test is inputted from the test mode selection external terminal 2. The decoder circuit 11 connects the signal line 71 to “H11”.
level, and the tristate buffer 31 is turned on.
The tristate buffer 41 is turned off. As a result, the circuit block 23 is separated from the circuit block 21 and connected to the test circuit 10. Therefore, a test input data pattern corresponding to the circuit block 23 is inputted from the test input data terminal 61. At this time, the tristate buffer 43 is in the ON state and outputs a test cover turn and an output cover turn corresponding to the circuit configuration of the circuit pro and block 23 to the test circuit 10 and other circuit blocks 25. The selector circuit 12 selects only the output of the circuit block 23 according to the signal line output from the decoder circuit 11 and outputs it to the test output data terminal.

With the above method, by separating the circuit block 23 from other circuit blocks and making it independent, it is possible to test the circuit block alone. Note that testing the circuit block alone can also be accomplished by following the above steps.

〔Effect of the invention〕

As explained above, the present invention provides a test circuit in a large-scale integrated circuit and provides a selector function therein, thereby separating and making multiple test paths independent and testing the circuit blocks under test individually. There is an effect that can be done.

[Brief explanation of drawings]

The drawing is a circuit diagram of a large-scale integrated circuit with a test circuit according to an embodiment of the present invention. 1... Line separating the inside and outside of the LSI, 2... External terminal for test mode selection, 10... Test circuit, 11...
Decoder circuit, 12... Selector circuit, 21-26.
...Circuit block, 31.32.41-44...Tristate buffer, 51.52...Inverter, 61
゜62...Test input data terminal, 63...Test output data terminal, 71...Signal line.

Claims (1)

[Claims] In a large-scale integrated circuit having a plurality of circuit blocks and a test circuit for testing the circuit blocks, a circuit wired or connected to a digital signal output section of the circuit block and a test input data output section of the test circuit. A state buffer is provided, and the test circuit is provided with a test mode selection external terminal for inputting serial test mode selection information and a decoder circuit for decoding the serial test mode selection information, and also inputs a digital output signal of the circuit block. The tristate buffer has a selector function that selects only the output of the circuit block by inputting the output signal of the decoder circuit as a control signal to the tristate buffer. A large-scale integrated circuit with a test circuit, characterized in that a plurality of test paths are separated and made independent so that circuit blocks under test can be individually tested.