JPH08286942A - Semiconductor circuit device - Google Patents

Abstract

PURPOSE: To provide a circuit with which each function block can be singly tested by providing a bus sharing the inputs/outputs of respective blocks and a circuit for switching a signal to be transmitted through the bus while using its external terminal at a microcomputer equipped with plural function blocks. CONSTITUTION: When testing a microcomputer core 1, a bus from a microcomputer core select terminal 3 of the external terminal to the microcomputer core is turned on and a bus from a random logic circuit select terminal 4 of the external terminal to a random logic circuit 2 is turned off. In this state, only the microcomputer core 1 can be tested and data are inputted through a data input terminal 5 of the external terminal, tristate inverter 9, shared bus 17, bus 24 and tristate inverter 10 to the microcomputer core 1 and outputted through the microcomputer core 1, tristate inverter 11, bus 23, shared bus 18 and tristate inverter 12 to a data output terminal 7 of the external terminal. When testing the random logic circuit 2, on the other hand, it can be singly tested by the similar method as well.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit device such as a microcomputer in which a microcomputer core and a random logic circuit are internally connected.

[0002]

2. Description of the Related Art FIG. 2 is a schematic circuit diagram of a conventional microcomputer incorporating a random logic circuit.
As shown in FIG. 2, the microcomputer core 1 and the random logic circuit 2 may be internally connected. In this microcomputer test, the random logic circuit 2
It is necessary to confirm that the signal input from the microcomputer core 1 to the microcomputer core 1 is normal and that the signal input from the microcomputer core 1 to the random logic circuit 2 is normal.

When testing the input signal to the microcomputer core 1, data is input from the data input terminal 27 to operate the random logic circuit 2 and the output 25 of the random logic circuit 2 is changed to perform the test. Further, the input 26 from the microcomputer core 1 to the random logic circuit 2 is required to operate the microcomputer core 1 to generate an input signal and output it from the data output terminal 28.

[0004]

However, in the above-described conventional configuration, when the random logic circuit 2 is tested, the microcomputer core 1 must be operated without fail, so the test takes time. Further, when the number of data input / output terminals 27 and 28 of the random logic circuit 2 increases, the wiring between the random logic circuit 2 and the microcomputer core 1 also increases, and there is a problem that the wiring efficiency deteriorates.

The present invention solves such a problem and provides a bus for sharing data input / output and a circuit for switching the input / output of the bus by an external terminal between the microcomputer core and the random logic circuit in the test mode. , It aims at improving wiring efficiency and facilitating individual test.

[0006]

In order to achieve the above object, the present invention provides a microcomputer in which a microcomputer core and a random logic circuit are internally connected, and in a test mode, the input of the microcomputer core and the random logic circuit A bus sharing the output, a bus sharing the output of the microcomputer core and the input of the random logic circuit,
It is characterized by having a circuit for switching the input / output of the bus by an external terminal.

[0007]

According to the present invention, the wiring efficiency of the microcomputer is improved by having a bus for sharing data input / output between the microcomputer core and the random logic circuit and a circuit for switching the input / output of the bus by an external terminal. It also facilitates individual testing.

[0008]

1 is a circuit diagram of a semiconductor circuit device according to an embodiment of the present invention, which is a microcomputer in which a microcomputer core 1 and a random logic circuit 2 are internally connected.

Here, 3 is an external terminal as a selection terminal of the microcomputer core 1, 4 is an external terminal as a selection terminal of the random logic circuit 2, 5 is an external terminal as a data input terminal to the microcomputer core 1, and 6 is Random logic circuit 2
Is an external terminal as a data input terminal to the microcomputer core, 7 is an external terminal as a data output terminal from the microcomputer core 1, and 8 is an external terminal as a data output terminal from the random logic circuit 2. 9 to 16 and 19 to 22 are tri-state inverters, which are tri-state inverters 9
To 12, 19, and 21 are provided by the L and H signals from the external terminal 3 and the tri-state inverters 13 to 16, 20, and 22.
Is ON / OF by the H and L signals from the external terminal 4, respectively.
Controlled to F state.

Buses 17 and 18 share the input (or output) of the microcomputer core 1 and the output (or input) of the random logic circuit 2 in the test mode. Reference numerals 23 and 24 are buses connecting the microcomputer core 1 and the random logic circuit 2.

The microcomputer core selection terminal 3, the random logic circuit selection terminal 4 and the tri-state inverters 9 to 22 of these external terminals constitute a switching circuit for the buses 17, 18, 23 and 24.

As shown in FIG. 1, the circuit of this embodiment includes a bus 23 which enters the random logic circuit 2 from the microcomputer core 1 through the tristate inverters 11 and 14, and a random logic circuit 2 through the tristate inverters 15 and 10. A bus 24 for entering the microcomputer core 1 is provided, a shared bus 18 connected to external data input / output terminals 6 and 7 between the tri-state inverters 11 and 14, and an external data input / output terminal 5 between the tri-state inverters 15 and 10. A shared bus 17 that connects to 8 is provided. The tri-state inverter has an external terminal 3
And 4, the terminal for selecting the microcomputer core 1 is 3, and the terminal for selecting the random logic circuit 2 is 4.

In actual use, the external terminals 5, 6,
Reference numerals 7 and 8 serve as terminals for the microcomputer core 1 and the random logic circuit 2.

Next, the operation of this embodiment will be described. When the microcomputer core 1 is tested, the "L" signal is input from the microcomputer core selection terminal 3 of the external terminals, and the microcomputer core 1 is tested.
To the random logic circuit selection terminal 4 of the external terminal, and the bus to the random logic circuit 2 is turned off.

That is, the tri-state inverter 9 or
12 is ON, tri-state inverters 13 to 16,
19, 21 are turned off. Therefore, in this state, only the microcomputer core 1 can be tested, and the data input is input to the microcomputer core 1 through the external data input terminal 5, the tri-state inverter 9, the shared bus 17, the bus 24 and the tri-state inverter 10. The data output from the microcomputer core 1 is output from the external data output terminal 7 via the microcomputer core 1, the tri-state inverter 11, the bus 23, the shared bus 18 and the tri-state inverter 12.

Next, when the random logic circuit 2 is tested, the random logic circuit selection terminal 4 of the external terminal is used.
Then, the "L" signal is input, the bus to the random logic circuit 2 is turned on, and the "H" signal is input from the microcomputer core selection terminal 3 of the external terminal to turn off the bus to the microcomputer core 1.

That is, the tri-state inverter 9 or
12, 20, 22 are OFF state, tri-state inverter 13
To 16 are turned on. Therefore, in this state, only the random logic circuit 2 can be tested, and the data input is performed via the data input terminal 6 of the external terminal, the tri-state inverter 13, the shared bus 18, the bus 23, and the tri-state inverter 14 for the random logic circuit 2. The data output is input to the random logic circuit 2, the tri-state inverter 15, the bus 24, the shared bus 17, the tri-state inverter 16, and the data output terminal 8 of the external terminal.
Will be output.

As described above, the individual test of the microcomputer having the microcomputer core and the random logic circuit is facilitated.

[0019]

As described above, in the semiconductor circuit device of the present invention, between the microcomputer core and the random logic circuit,
By having a bus that shares data input / output and a circuit that switches the input / output of the bus by an external terminal, individual tests of a microcomputer having a microcomputer core and a random logic circuit can be easily performed, and a microcomputer The wiring efficiency of can be improved.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a semiconductor circuit device according to an embodiment of the present invention.

FIG. 2 is a schematic circuit configuration diagram of a microcomputer including a conventional random logic circuit.

[Explanation of symbols]

1 ... Microcomputer core, 2 ... Random logic circuit, 3
… Microcomputer core selection terminal, 4… Random logic circuit selection terminal, 5… Microcomputer core data input terminal, 6… Random logic circuit data input terminal,
7 ... Data output terminal from microcomputer core, 8 ... Data output terminal from random logic circuit, 9-16, 19-
22 ... Tri-state inverter, 17, 18 ... Shared bus,
23, 24 ... Bus.

Claims (1)

[Claims] 1. A microcomputer in which a microcomputer core and a random logic circuit are internally connected, a bus sharing an input of the microcomputer core and an output of the random logic circuit in a test mode, and an output of the microcomputer core and a random logic. A semiconductor circuit device comprising: a bus that shares an input of a circuit; and a circuit that switches input / output of the bus by an external terminal.