JPH10123213A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the semiconductor integrated circuit, which can perform the logic function test readily by suppressing the increase of the circuits required for switching terminals to a minimum without increasing the number of the terminals. SOLUTION: A plurality of input/output terminals 40-47 connected to a plurality of ports 11 and 12 and an LSI tester provided in a semiconductor integrated circuit, a selector 20, which is inserted between these ports and the input/output terminals, and a register 30, which controls the switching state of the selector 20 based on the present value, are provided. The register 30 connects the port 11 to the input/output terminals 40-43 when the preset value is '1' by a reset terminal 50 and connects the port 12 to the input/output terminals 40-43 when the present value of the register 30 is '0' through the CPU 10. A special terminal for selective switching is not required, and the test with the LSI tester having a small number of terminals can be performed without enlarging the circuit scale.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a logic integrated circuit structure having a large number of input / output terminals, and more particularly to enabling a logic function test to be easily performed using an LSI tester having a small number of terminals. The present invention relates to a semiconductor integrated circuit.

[0002]

2. Description of the Related Art When a logic function test of a semiconductor integrated circuit is performed, it is necessary to connect input / output terminals provided on the semiconductor integrated circuit to an LSI tester. For this reason, when testing a semiconductor integrated circuit in which the number of input / output terminals has been increased in recent years, the number of terminals corresponding to this is L
It is necessary to prepare an SI tester, which is not economically effective. Therefore, in order to enable testing of a semiconductor integrated circuit having more terminals than the number of terminals of the LSI tester, a semiconductor integrated circuit in which input / output terminals are switched in the semiconductor integrated circuit has been proposed. For example, FIG. 5 shows an example of a semiconductor integrated circuit having a reduced number of test terminals.
No. 3874.

In this semiconductor integrated circuit, a test input terminal 1
13, a test output terminal 623, and a plurality of signal input terminals 6.
14 to 616 and a plurality of signal output terminals 624 to 626
And latch circuits 617 to 619 having a structure for latching by feeding back two stages of inverters and connecting one to each of signal input terminals 614 to 116, and one terminal for each of these latch circuits Input analog switches 620-622, the other terminal of which is connected to the test input terminal 613, and one of the signal output terminals 624-626.
And one terminal is connected to the test output terminal 6
Output analog switches 627-629 connected to 23
And an input selection signal generator 605 as means for sequentially selecting input analog switch control signals 702 to 704 from one clock signal 701, and output analog switches 627 to 62 by one clock signal 709.
And an output selection signal generator 606 as means for selecting the nine control signals 710 to 712 in order and outputting an output signal to the test output terminal 623.

The semiconductor integrated circuit employs a well-known scan path method, in which a shift control signal 706 is activated, and a shift input signal is synchronized with a shift clock signal 707 from a shift input terminal 608. 708, the scan path constructing unit 604 that operates all the internal sequential circuits as a series of shift registers, and the input unit combination logic circuit 602 and the output of the sequential circuit that are data inputs of the sequential circuit during normal operation are logically connected. An output combination logic circuit 603 for performing an operation is provided.

Therefore, in this semiconductor integrated circuit, the input selection signal generator 605 receives the input selection clock signal 701 from the clock input terminal 607 and opens and closes the input analog switches 620-622. 704 are selected in order. Input analog
The switches 620 to 622 are connected to the input selection signals 702 to 702, respectively.
When 704 is selected, the test input signal 705 input to the test input terminal 613 is forcibly latched by the latch circuits 617-61.
Make a path to write to 9. Similarly, the output side controls the output analog switches 627 to 629 by selecting the output selection signals 710 to 712 from the output selection signal generator 606 according to the output selection clock signal 709, and outputs the test output signal 713 to the test output terminal 623. Output. As described above, the test of the sequential circuit can be performed independently and the state of the sequential circuit can be freely set, so that the test of the logic circuit can be efficiently performed.

[0006]

However, this semiconductor integrated circuit has dedicated terminals 607-6 as signal terminals for controlling an operation for selecting an input / output terminal.
Since it is necessary to provide 10, 612, 613, and 623, these terminals are increased in addition to the existing terminals, and the configuration of the semiconductor integrated circuit is complicated. Further, since a plurality of dedicated circuit units for switching are required, the overall circuit scale of the semiconductor integrated circuit also becomes large. As described above, in the conventional semiconductor integrated circuit, since the number of terminals is increased and the circuit scale is increased, there is a problem that the integration and miniaturization of the semiconductor integrated circuit are hindered.

An object of the present invention is to provide a semiconductor integrated circuit capable of easily performing a logic function test without increasing the number of terminals and minimizing an increase in circuits required for switching terminals. It is to provide a circuit.

[0008]

A plurality of signal terminals connected to an internal circuit provided in a semiconductor integrated circuit, a plurality of input / output terminals connected to an external device, these signal terminals and the input / output terminals are provided. A selector that is interposed between and selectively switches connection between these signal terminals and input / output terminals, and a register that controls a switching state of the selector based on a set value, The register is configured such that its set value can be changed and set by an existing terminal provided in the semiconductor integrated circuit and the internal circuit.

Here, the register is a reset terminal and a CPU.
, A reset value is set by a reset signal from a reset terminal, a set value is changed by an address output from the CPU, and a selector is switched by an output based on these set values. Alternatively, the register is connected to the reset terminal and a part of the input / output terminal, a reset value is set by a reset signal from the reset terminal, and a predetermined set value is set by a signal from the input / output terminal. Based on the output, the selector is switched. Some of the input / output terminals are input / output terminals that are not connected to the internal circuit when the register is in the reset state. Further, the selector includes a plurality of signal terminals connected to an internal circuit and a plurality of switch elements interposed between the plurality of input / output terminals, respectively, and selectively turns on the switch elements by an output from a register. , And is configured to be turned off.

[0010]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a main part of a semiconductor integrated circuit according to a first embodiment of the present invention.
The semiconductor integrated circuit includes a CPU 10 and two general-purpose input / output ports connected to the CPU 10 by a bus, here, a 4-bit general-purpose input / output port 11 connected to the 8-bit bus of the CPU 10 by 4 bits each. , 12
And a selector 20 connected to the respective terminals of the input / output ports 11 and 12 for selecting the connection state of these terminals, and a register 30 for controlling the selector 20
And Then, 4 × 2 input / output terminals 40 to 43 and 44 to 47 connected to the selector 20, respectively.
And a reset terminal 50 to which a signal for resetting the CPU 10 and the register 30 is input. The register 30 is also connected to the CPU 10 via a bus so that data can be input through the CPU 10.

FIG. 2 is a circuit diagram of an example of the selector 20. The selector 20 includes 16 transfer gates 200 to 215 and an inverter 216. The transfer gates 200 to 215 are:
Each pair has a 2 × 8 configuration, and one end of each pair is commonly connected to each terminal on the bus side of the CPU 10. The other end of each of the transfer gates 200 to 215 has one terminal 40 to
43, and the other is connected to terminals 44-47. Further, the inverter 216 is connected to the register 30
Is connected to one of the control terminals of the transfer gates of each of the sets, and an inverted signal of the output of the register 30 is input to the output terminal of the inverter 216. The other is connected to the input terminal side of the inverter 216, and the output of the register 30 is directly input.

In this selector 20, the register 30
Is "0", the transfer gate 200,
203, 204, 207, 208, 211, 212, 2
The inverted signal “1” is input to 15 and these are turned on, and the port 11 is connected to the input / output terminals 40 to 43, and the port 12 is connected to the input / output terminals 44 to 47. When the output of the register 30 is "1", the transfer gates 201, 202, 205, 206, 209, 2
10, 213, 214, their outputs are input as they are and these are turned on, and the port 11 and the input / output terminals 44 to 4
7. The port 12 is connected to the input / output terminals 40 to 44, respectively. When the reset terminal 50 is set to "1", the register 30 is reset to "0" in the initial state.

A description will be given of a method of testing the logic function of the ports 11 and 12 for the semiconductor integrated circuit having the above configuration. Here, since the number of terminals of the LSI tester is smaller than the number of input / output terminals of the semiconductor integrated circuit, the input / output terminals 40 to 43 and the reset terminal 50 are connected to the LSI tester. 47 is not connected to the LSI tester. First, "1" is input to the reset terminal 50 to initialize the CPU 10 and the register 30. By resetting the register 30, the value of the register 30 becomes "0", and the input / output terminals 40 to 43 are connected to the port 11 as shown in FIG. Therefore, the logical function test of the port 11 can be performed through the input / output terminals 40 to 43. When the logical function test of the port 11 is completed, the address of the register 30 is output from the CPU 10 and the value of the register 30 is rewritten to “1”. As a result, the input / output terminals of the port 11 and the port 12 are switched, and the input / output terminal 40
To 43 are connected to the port 12, and the logical function test of the port 12 can be performed through the input / output terminals 40 to 43.

According to the first embodiment, even when the number of terminals of the LSI tester is smaller than the number of terminals of the semiconductor integrated circuit on which the logical function test is performed, the terminals of the semiconductor integrated circuit are connected to L
By changing the terminals by a switching operation inside the semiconductor integrated circuit without changing the terminal connection of the SI, the logical function test of all the input / output terminals can be performed. In this case, a reset signal is input to the existing reset terminal 50 to reset the register 30,
Just rewrite the value of register 30 through U10,
Since the above-described terminal switching can be realized by operating the selector 20, it is not necessary to newly provide a terminal for switching, and it is not necessary to increase the number of terminals.

FIG. 3 is a block diagram of a main part of a semiconductor integrated circuit according to a second embodiment of the present invention. In the figure, the same parts as those in the first embodiment are denoted by the same reference numerals, but the configuration of the semiconductor device of the present embodiment is different from that of the first embodiment in that the register 30 is connected to the CPU 10. Instead, it is connected to the port 12 and the value can be rewritten through the port 12. It is assumed that the configuration of the selector 20 is the same as that shown in FIG.

FIG. 4 is a circuit diagram of the register 30 according to the present embodiment. The register 30 includes a D flip-flop 301 and an AND circuit 302.
The terminal is a part of the port 12, here the input / output terminal 4
4 is connected, and the reset terminal 50 is connected to the clock terminal. The output and the reset terminal 50 are connected to the
The input is input to the D circuit 302, and the output is input to the selector 20. In this configuration, when “1” is output from the reset terminal 50 (reset state),
The output of the D circuit 302, that is, the output of the register 30, becomes "0". Therefore, as shown in FIG. 2, in the selector circuit 20, the port 12 is connected to the input / output terminals 44 to 47. At this time, the input / output terminal 44 connects the register 30
When the reset terminal 50 is set to "0" (the reset is released), the value of the input / output terminal 44 is input to the register 30 through the port 12, and the output of the D-flip-flop 301, that is, the input / output The value at the terminal 44 becomes the output of the AND circuit 302, that is, the register 30 as it is.

According to this configuration, at the time of the logical function test of the ports 11 and 12 for the semiconductor integrated circuit,
Although the number of terminals of the SI tester is smaller than the number of input / output terminals of the semiconductor integrated circuit, it is assumed here that the input / output terminals 44 are connected to the LSI tester in addition to the input / output terminals 40 to 43 and the reset terminal 50. . Here, reset terminal 5
"1" is input to "0" to initialize the CPU 10 and the register 30. By resetting this register 30,
The value of the register 30 becomes “0” and the input / output terminals 40 to 4
3 is connected to the port 11 and the input / output terminal 4
The logical function test of the port 11 can be performed through 0 to 43. When the logical function test of the port 11 is completed, “0” is input to the reset terminal 50 and the input / output terminal 44
"1" is input. As a result, the value of the register 30 becomes "1", and this value is input to the selector 20, so that the input / output terminals of the port 11 and the port 12 are exchanged. In this state, the logical function test of the port 12 can be performed through the input / output terminals 40 to 43.

Also in the second embodiment, even when the number of terminals of the LSI tester is smaller than the number of terminals of the semiconductor integrated circuit on which the logic function test is performed, the connection between the terminal of the semiconductor integrated circuit and the terminal of the LSI is changed. In addition, by exchanging the terminals by the switching operation inside the semiconductor integrated circuit, the logical function test of all the input / output terminals can be performed. In this case, a reset signal is input to the existing reset terminal 50 to reset the register 30, and
By simply rewriting the value of the register 30 through the input / output terminal 44 that is not connected to the SI tester, the selector 20 can be operated and the above-described terminal switching can be realized.
There is no need to provide a new terminal for switching,
There is no increase in the number of terminals. In addition, when the value of the register 30 is rewritten, it is not necessary to input a value from the CPU 10, so that the number of address decoder circuits can be reduced.

In the second embodiment, when "1" is input from the reset terminal 50, the input / output terminal 4
Although the value of the register 30 is set by inputting a value from 4, if it is detected that the input / output terminal 44 of the port 12 is not used as the input / output port with the value of the terminal other than the reset terminal or the value of the register, for example. Alternatively, the reset terminal may not be used. Further, in the present invention, the number of bits of the register can be increased to change the input / output terminals in three or more ways, or the terminals other than the general-purpose port such as the reset terminal and the clock output terminal can be replaced.

[0020]

As described above, in the semiconductor integrated circuit of the present invention, the selector is inserted between the signal terminal connected to the internal circuit and the input / output terminal connected to the external device, and the set value is set. Accordingly, the selector is provided with a register for controlling the connection between the signal terminal and the input / output terminal, and the setting value of this register can be changed from the existing terminal. Thus, the signal terminal and the input / output terminal can be selectively switched, and a test using an LSI tester with a small number of terminals can be realized. Therefore, there is no need to provide dedicated test terminals, and it is not necessary to provide a large number of dedicated test circuits, thereby simplifying the configuration of the semiconductor integrated circuit and minimizing the increase in circuit scale. A semiconductor integrated circuit that can easily perform a logical function test using a small number of LSI testers can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an internal configuration of a selector.

FIG. 3 is a block diagram showing a configuration of a main part of a second embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating a configuration of a register according to a second embodiment.

FIG. 5 is a block diagram illustrating an example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 CPU 11, 12 port 20 Selector 30 Register 40-47 I / O terminal 50 Reset terminal 200-215 Transfer gate 216 Inverter 301 D-flip-flop 302 AND circuit

Claims (5)

[Claims] 1. A plurality of signal terminals connected to an internal circuit provided in a semiconductor integrated circuit, a plurality of input / output terminals connected to an external device, and interposed between the signal terminals and the input / output terminals. A selector for selectively switching the connection between these signal terminals and the input / output terminals, and a register for controlling a switching state of the selector based on a set value, wherein the register is provided in the semiconductor integrated circuit. A semiconductor integrated circuit wherein the set value can be changed and set by an existing terminal and the internal circuit. 2. A register is connected to a reset terminal and a CPU, a reset value is set by a reset signal from the reset terminal, a set value is changed by an address output from the CPU, and a selector is set by an output based on these set values. 2. The semiconductor integrated circuit according to claim 1, wherein the switching is performed. 3. A register is connected to a reset terminal and a part of an input / output terminal, a reset value is set by a reset signal from the reset terminal, and a predetermined value is set by a signal from the input / output terminal. 2. The semiconductor integrated circuit according to claim 1, wherein the selector is switched by an output based on the set value. 4. The semiconductor integrated circuit according to claim 3, wherein a part of the input / output terminal is an input / output terminal that is not connected to an internal circuit when the register is in a reset state. 5. The selector includes a plurality of signal terminals connected to an internal circuit and a plurality of switch elements interposed between the plurality of input / output terminals, respectively, and selects the switch element by an output from a register. 5. The semiconductor integrated circuit according to claim 1, wherein said semiconductor integrated circuit is configured to perform an on / off operation.