JPH03174634A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To omit an external pin that sets only an internal mode by providing the internal mode setting storage circuits on the data and address pins in a normal operation mode, latching the signals inputted from those external pins in the storage circuits, and using the output signals received from these storage circuits as the internal mode setting signals. CONSTITUTION:In a normal mode the data inputted via a data pin 19a are latched synchronously with a clock signal and fetched by a microprocessor via a data input line 21b. Then the processed data are outputted via a data output line 21a and taken out via the pin 19a. In a test mode an internal mode setting signal is inputted via the pin 19a synchronously with a resetting signal 20 and then latched by a storage circuit 25 added to the pin 19a. The output signal 24 of the circuit 25 is used as a scan path selecting signal. Thus it is possible to omit an exclusive external pin that sets an internal mode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit having a function of operating in a mode different from normal operation, such as a microprocessor with a scan scan method test function.

[Conventional technology]

In general, an LSI such as a microprocessor is composed of a large number of combinational circuits and sequential circuits, and includes several functional blocks composed of a plurality of such combinational circuits and sequential circuits. In such microprocessors, in order to efficiently test the number of logic gates that are increasing as manufacturing technology improves, a method has been adopted that uses a circuit that allows independent testing of each functional block. One such method is the scan canvas method, which creates a single serial scan canvas by converting registers that store input and output data of functional blocks into shift registers and connecting them in series. By attaching an external pin for the hitch blade, it is possible to set values to the input register of the function block from the outside and read the hani from the output register. In this method, the microprocessor has a test mode different from the normal operation mode to perform tests, and in the test mode, the functions of the input and output registers of the i-function block are switched. In this way, you can easily test a functional block by setting a combination of test patterns in the input register of the functional block to be tested through the scan canvas, and after the value is processed by the functional block, the output data is read externally and observed. Can be tested.

FIG. 3 shows an embodiment of a conventional microprocessor that performs a scan path system test.

In Fig. 3, 00) is a conventional microprocessor, α
D is a multiplexer circuit (19a, 19b, . . .
, 19n) is an external bin for selecting a scan path, Ol is an external pin for switching between normal mode and test mode, (14
a14b, ..., 14n) are functional blocks, (16a
, 16b16r) are the input and output registers of the functional block, (15a, 15b, ..., 15n) are the scan path, 021 is the input bin of the scan path, 0 is the output bin of the scan path, (19a, 19b, --- ,1
9n) is a human output pin for data and address, and (20) is a reset signal input pin.

Scanvase (15a, 15b, ..., 15n)
are the input and output registers of the function block (16a, 1
6b, . . . , 16r) are connected in series. Data bins and address bins (19a, 19b).

The signal line from 19n) is connected to the human output register of the functional block (16a, 16b, . . . , 16n).

The signal from the external pin 08 for mode switching is sent to the registers (16a, 16b, . . . , 1) on the scan path.
6n). The reset signal t20) is input to all circuits that perform initialization within the microprocessor.

A scan path selection signal is input to the multiplexer circuit 0υ. The microprocessor 00) consists of several functional blocks and sequential circuits, and is passed through a scan canvas to test each functional block.

FIG. 4 shows the input and output registers (16a, 16b) of the functional blocks used in the scan path method.

In FIG. 4, (Ia, Ib) are multiplexer circuits,
(2a, 2b) is the D latch, (3) is the data shifted in by the scan canvas, (4a, 4b) is the output data from the function block connected to the previous stage, (5a.

5b) is the input data to the next functional block, (6)
is a mode signal that switches between normal operation and test operation, (7
) is a clock signal, and (8) is data shifted out through the scan canvas.

Next, the operation will be explained. First, the operation of a conventional microprocessor with a scan path type test function shown in FIG. 3 will be explained. Set the microprocessor's internal mode to test mode to perform a test. By inputting the test mode setting signal from the external pin αO, the input and output registers (16a,
16b, . . . , 16r) are brought into a state where they can operate as shift registers for the scan canvas instead of operating as registers in the normal operation mode. In this state, by applying a clock signal to the shift register, the bit string of the test pattern is shifted in from the input pin (2) and set in the input register of the functional blocks (14a, 14b, . . . , 14n). After that, when a signal for setting the normal operation mode is input to the external bin αω, the test pattern sent to the scan canvas is input to the function block (14a) to be tested, and after processing the data, the function block (14a)
are latched into the output registers (16d, . . . , 16f). In order to retrieve the test results, the scan path (15
Shift out the test results through a). The shifted out data is input to the multiplexer circuit 0]), and external pins (17a, 17b) for scan path selection are input.

, 17n) causes the scan canvas (15a) to
is selected and the test result is retrieved from scan output bin α. Similarly, an external pin (17
a 17b, . . . , 17n), and select the scan canvas (15a, 15b).

By reselecting the function block (15n), the function block (14a
.

14b, . . . , 14n) can be sequentially examined.

Next, the operation of the registers (16a, 16b) shown in FIG. 4 will be explained. In FIG. 4, when the mote signal (6) is 0, it is the normal operation mode, and when it is 1, it is the test mode. In normal operation mode, data (4a, 4b) selected by the multiplexer circuit (la, lb) in synchronization with the clock signal (7) is latched into the D latch (2a, 2b), and the launched signal is transferred to the next stage. These are the input signals (5a, 5b) to the functional blocks. In test mode, the multiplexer circuit (1) is synchronized with the clock signal (7).
The data (3) input through the scan path selected by a) is latched by the D-7ch (2a), and furthermore, at the D-launch (2b), the output of the D-launch (2a) is similarly connected to the clock signal (7). ) is latched in synchronization with By switching the inputs using the multiplexer in this manner, a shift register is configured on the scan path in the test mode. In this way, the function of the human output register on the scan path provided in each functional block is switched by a signal from the external pin 081, and a functional block test can be easily performed.

By repeating this and testing all functional blocks within the microprocessor, the entire microprocessor can be tested.

[Problem to be solved by the invention]

As mentioned above, the conventional microprocessor has a scan path input pin (2), a scan path output pin 03),
Scan path selection pins (17a, 17b).

17n) etc., an external pin dedicated to the test mode was required. Therefore, there is a problem in that as the number of functional blocks to be tested increases, a large number of external pins dedicated to these internal mode settings are required.

This invention was made to solve the above-mentioned problems, and it is possible to eliminate the need for a dedicated external pin for setting the internal mode when testing the functional blocks of a microprocessor using the scan path method. With the goal.

[Means to solve the problem]

The microprocessor according to the present invention provides a memory circuit for external pins such as data pins and address bins used in normal operation mode, and latches the values of these external pins in the memory circuit in synchronization with a reset signal. The outputs of these memory circuits are used as signals for internal mode setting.

[Effect]

According to this invention, a memory circuit for internal mode setting is provided on the data pin and address pin in the normal operation mode, and signals input from these external pins are latched in the memory circuit, and output signals from these memory circuits are internally stored. By using this signal as a mode setting signal, a dedicated external pin for internal mode setting can be made unnecessary.

〔Example〕

FIG. 1 shows a microprocessor showing an embodiment of the present invention. In the figure, 00 is a multiplexer circuit for selecting a scan path, (25) is a memory circuit that latches the scan path selection signal, 0 is an external pin for inputting a test mode setting signal, (14a, 14b, ・
, 14n) are function blocks, (16a, 16b).

, 16r) is a shift register, (15a, 15
b15n) is the scan path, 02) is the input pin of the scan path, α is the output bin of the scan path, (19a, 1
9b19f) are data pins, address bins, etc. used in the normal operation mode, (20) is a reset signal input pin, and 00) is a microprocessor according to the present invention.

The microprocessor 00) is a functional block (14a).

14b, ..., 14n) and shift register launch (1
6a, 16b16r) or scan path (15a,
15b15c), and also includes a storage circuit (25) for scan path selection signals. Data pins and address bins (19a, 19b, ..., 19n)
The signal line from the function block input/output register (16a
, 16b.

16n). The signal from external pin 0[0 for mode switching is a register on the scan path (16a
16b,..., 16n). The reset signal (20) is input to all circuits that perform initialization within the microprocessor sensor. The external pins dedicated to the test mode are the scan path input pin 02), the scan path output bin α3), and the external pin 08) for internal mode switching. FIG. 2 shows in detail the added data pin (19a) of the memory circuit shown in FIG.
19a) is the data pin, (20) is the reset signal, 0
0) is a microprocessor according to the present invention, (21a)
is the data output signal used in normal operation mode, (21
b) Input signal (23) of data used in the normal operation mode is a signal for controlling the output of data used in the normal operation mode, (25) is a memory circuit added to the data pin (19a), ( 24> is the memory circuit (25)
This is the output signal from .

Next, the operation will be explained. In Figure 1, first, a scan canvas selection signal is input from external pins (19a, 19b, . . . , 19n) such as data bins and address pins, and is synchronized with a reset signal (20) built into the microprocessor. The data is stored in the memory circuit (25). The signal causes the function blocks (14a, 14b14
n) Scan canvas (15a, 15b) provided in units.

15n) can be selected.

Next, to perform a test, the microprocessor's internal mode is set to test mode. By inputting the test mode setting signal from the external pin 08), the input and output registers (16a, 16b) of the functional block are controlled.

, 16r) is not the register operation in normal operation mode,
Make it ready to operate as a scan canvas shift register. In this state, by inputting a clock signal to the shift register, the bit string of the test pattern is shifted in from the input pin 021, and the bit string of the test pattern is input to the functional blocks (14a, 14).
b, . . . , 14n) input registers.

After that, when a signal for setting the normal operation mode is input to the external pin 08), the test pattern set in the scan canvas is input to the function block (14a) to be tested, and after processing the data, the output register of the function block (14a) (16d, . . . , 16f) is lunched.

In order to retrieve the test result, a signal for setting the test mode is input again from the external pin αω to put the register on the scan canvas into the shift register operating state. In this state, the test result is shifted out through the scan canvas (L5a) by inputting a clock signal to the shift register (16a16f). The shifted out data is input to the multiplexer circuit O1l, and the data is input to the scan canvas (15) by a signal from the scan canvas selection memory circuit (07).
a) is selected and the test result is retrieved from the scan output pin 031. Unlike the conventional example, the external pins required for the test mode are the scan canvas input pin (8),
There are only 3 pins: scan canvas output pin (9) and pin output for internal mode switching.

Next, the operation of the data bin to which a storage circuit is added will be explained in FIG. In normal mode, the data bin (
The data input from 19a) is latched in synchronization with the clock signal and taken into the microprocessor from the data input line (21b). The processed data is output from the data output line (21a) and taken out from the data bin (19a). In the test mode, a signal for internal mode setting is input from the data bin (19a) in synchronization with the reset signal Qal, and the signal is latched into the memory circuit (25) attached to the data bin (19a), and its output signal is (
24) is used as the scan canvas selection signal. At the time of reset, the data input signal (21b) is always in the l1i-Z state, that is, the input state, so that the internal mode setting signal 9 can be input from the data bin (19a). This memory circuit is
When the reset signal (2) is It i B h, data is latched, and the latched data signal can be used as a scan canvas selection signal of the microprocessor.

In the above embodiment, an internal mode setting launch circuit is provided in the data bin during normal operation, but a similar circuit can be constructed in an address pin or any other insignificant external pin.

〔Effect of the invention〕

As described above, according to the present invention, by generating an internal mode setting signal using the output signal of the memory circuit provided in the data bin, address pin, etc. during normal operation, it is possible to replace the scan canvas of the conventional microprocessor. This has the effect of making it possible to test the microprocessor without the need for a dedicated external pin required for selection.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a microprocessor showing an embodiment of the present invention, Fig. 2 is a storage circuit diagram added to a data bin shown to explain Fig. 1 in detail, and Fig. 3 is a functional processor circuit diagram. FIG. 4 is a circuit diagram of a microprocessor showing a conventional embodiment. In the figure, (15a, 15b, ..., 15n) are scan paths, (19a, 19b, ..., 19n)
is an external pin for inputting data or control signals, I20)
is the reset signal input pin, (25) is the external pin (19a
, 19b, . . . , 19n). In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] An external pin that inputs a reset signal that initializes the internal operating state of the LSI, and an external pin that can input or output data or control signals, and has at least two different types of internal functions. the data or control signal, the reset signal being input from the external pin, or a reset signal internally generated using the reset signal; has a memory device that stores data input on an external pin that inputs or outputs the data, and uses the output signal of the memory device to set the operating state of the circuit that has two or more different operating states. A semiconductor integrated circuit characterized by: