JP3119568B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a standard cell type semiconductor integrated circuit including a test circuit and a plurality of macro circuits connected to each other.

[0002]

2. Description of the Related Art As a test method performed in a semiconductor integrated circuit of a standard cell system composed of a plurality of interconnected macro circuits, there are the following methods. First, a system that tests the state of interconnection between the built-in macro circuits by operating all the circuits that make up the semiconductor integrated circuit, inputting signals from external terminals, and observing the output signals at this time. There is a test.

Hereinafter, the above-described system test method will be described. FIG. 4 is a block diagram showing a configuration of a semiconductor integrated circuit composed of two macro circuits. In the figure, a semiconductor integrated circuit 59 includes a macro circuit 60 and a macro circuit 61, and external terminals 62 to 65 of the semiconductor integrated circuit 59 are connected to input terminals 66 to 6 of the macro circuit 60.
9 respectively.

The output terminals 70 to 7 of the macro circuit 60
3 is internally connected to input terminals 74 to 77 of the macro circuit 61, respectively. The output terminals 78 to 81 of the macro circuit 61 are connected to the external terminals 82 to 8 of the semiconductor integrated circuit 59.
5 respectively. When testing the semiconductor integrated circuit 59, a predetermined test pattern signal is input from the external terminals 62 to 65, and a signal output from the external terminals 82 to 85 is observed to test the internal operation from the outside. Can be.

Here, when a system test is performed on a semiconductor integrated circuit, in order to sufficiently test the functions of a plurality of mounted macro circuits, only some of the externally connected terminals are used as terminals of each macro circuit. Utilizing these, the functions of the macro circuits and the connection test between the macro circuits must be tested. Then, a complicated test pattern (test signal) must be input to the input terminal of the macro circuit via the external terminal, and the state of the output terminal of the macro circuit must be set.

For this reason, when a macro circuit constituting a semiconductor integrated circuit is large-scale, an enormous test pattern is required to extract all output states in a test. This becomes remarkable as the scale of the macro circuit increases and the circuit configuration becomes complicated. As a result, there is a problem that it takes a long time to create an enormous test pattern, which leads to an increase in a product development period.

Further, when the number of test patterns becomes enormous, the test time of an actual semiconductor integrated circuit also increases, and as a result, there is a problem that the product cost increases. In the method described above, the macro circuit 6
It is not possible to test the function of each of 0 and 61 alone. Here, if all the terminals of the macro circuits 60 and 61 can be taken out and tested individually, the functions of the macro circuits 60 and 61 alone can be tested individually.

This is called a macro separation test, in which a mode is set so that the terminals of each macro circuit are assigned to the external terminals of the semiconductor integrated circuit, and a signal is applied from the external terminal and each macro circuit is directly transmitted from the external terminal. By observing a single output, each macro circuit is individually tested. Hereinafter, this macro separation test will be described with reference to FIG. FIG. 5 is a block diagram showing a configuration of a conventional semiconductor integrated circuit incorporating a macro separation test circuit.

Referring to FIG. 1, a semiconductor integrated circuit 86 includes macro circuits 87 and 88 and a test mode control circuit 126. Input terminals 93 to 96 of the macro circuit 87
Are connected to external terminals 89 to 92 of the semiconductor integrated circuit 86, respectively. The normal mode output terminals 101 to 104 of the macro circuit 87 are internally connected to the normal mode input terminals 109 to 112 of the macro circuit 88. And
Output terminals 113 to 116 of the macro circuit 88 are connected to external terminals 117 to 120 of the semiconductor integrated circuit 86, respectively.

On the other hand, test mode output terminals 97 to 100 of the macro circuit 87 are connected to external terminals 121 to 124. The test mode input terminals 105 to 108 of the macro circuit 88 are connected to external terminals 130 to 133. Here, the test mode control circuit 126 outputs a control signal according to a mode switching signal input from the outside. The macro circuit 87 is controlled by receiving this control signal via the control signal line 125, and the output destination of the output signal is switched. That is, the output is switched between the normal mode output terminals 101 to 104 and the test mode output terminals 97 to 100.

Similarly, in the macro circuit 88, the switching operation is controlled by the control signal output from the test mode control circuit 126 via the control signal line 127, and the input signal is switched. That is, according to a control signal from the test mode control circuit 126, switching between input from the normal mode output terminals 109 to 112 and input from the test mode output terminals 105 to 108 is switched.

Next, the operation of the semiconductor integrated circuit 86 will be described. In the normal operation mode, when a control signal for setting the normal operation mode is input from the external control terminals 128 and 129, the test mode control circuit 126 set to the normal operation thereby controls the control signal lines 125 and 1.
The macro circuit 8 is controlled by a control signal output through the
7 and 88 are both set to the normal operation mode.

The output signal of the macro circuit 87 is input to the normal mode input terminals 109 to 112 of the macro circuit 88 via the normal mode output terminals 101 to 104, respectively. Further, test mode output terminals 97 to 100, 105 to 105 of the macro circuit 87 and the macro circuit 88, respectively.
Reference numeral 108 denotes a cut-off state, in which a signal is not input / output.

Next, the operation of each of the macro circuits 87 and 88 in the separation test mode will be described. First, when a separation test of the macro circuit 87 is performed, the normal mode output terminals 101 to 104 of the macro circuit 87 and the macro circuit 88 are controlled by a control signal output from the test mode control circuit 126 via the control signal lines 125 and 127. Of the normal mode input terminals 109 to 112 are cut off. Test mode output terminals 97 to 100 of macro circuit 87 and test mode input terminals 105 to 108 of macro circuit 88
Is set to the active state.

The test of the macro circuit 87 alone can be performed by inputting a test signal from the external terminals 89 to 92 and observing output signals output from the external terminals 121 to 124. Similarly, the external terminal 130
１３133, a test signal is input from an external terminal 117.
By observing the signals output from １２０120, a test of the macro circuit 88 alone can be performed.

As described above, each macro circuit is provided with a normal mode terminal and a test mode terminal, and switching between the normal mode terminal and the test mode terminal inside the semiconductor integrated circuit is performed by a mode switching signal input from the outside. By doing so, each macro circuit alone can be tested from external terminals of the semiconductor integrated circuit.

[0017]

Conventionally, the above-mentioned configuration has the following problems.
As described above, in the conventional isolation test of a semiconductor integrated circuit, unlike the system test, the function of each macro circuit can be tested as a single unit. However, in order to test the connection state between the macro circuits, it is necessary to perform the above-described system test.
That is, conventionally, there has been a problem that a system test must be performed after all in order to test a connection state between macro circuits.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to simplify a test performed in a semiconductor integrated circuit using a standard cell system.

[0019]

A semiconductor integrated circuit according to the present invention has a first macro circuit having a first circuit block having a macro function and a second macro circuit having a second circuit block having a macro function. In the standard cell type semiconductor integrated circuit in which the macro circuits of the first and second macro circuits are connected to each other via a connection between the macro circuits, the terminal of the first macro circuit on the side of the second macro circuit is connected to the terminal of the second circuit block. Or a first switching circuit for switching between connecting directly to a first external test mode terminal without connecting to a terminal of the second circuit block in the second macro circuit,
First, the first circuit block is provided between the macro circuit connection and the terminal of the second circuit block and the first
The terminal on the second macro circuit side of the macro circuit is connected to a first test mode terminal via a connection between macro circuits and a first switching circuit.

The semiconductor integrated circuit according to the present invention has a macro function.
Macro circuit incorporating a first circuit block having
And a second circuit block having a second circuit block having a macro function.
The two macro circuits are connected to each other via the macro circuit connection.
Continued standard cell type semiconductor integrated circuit
Terminal of the first macro circuit on the side of the second macro circuit.
Connected to the terminal of the second circuit block or the second circuit block.
1st test module directly outside without connecting to
A first switching circuit for switching between connection to a load terminal
In the second macro circuit and the connection between the macro circuits
Between the wire and the terminal of the second circuit block,
The terminal on the first macro circuit side of the second macro circuit is connected to the first macro circuit.
Connected to the terminal of the circuit block or the first circuit block
The second test mode directly outside without connecting to the terminal of
A second switching circuit for switching whether to connect to the terminal
Within one macro circuit and the connection between the macro circuits.
The first circuit block is provided between the first circuit block and a terminal of the first circuit block.
When testing the lock alone, the terminal of the first circuit block
Is transmitted through the second switching circuit to the second macro circuit of the first macro circuit.
And the second macro
(B) The terminal on the circuit side is the connection between the macro circuits and the first switching
Connected to the first test mode terminal through the circuit,
When testing a single circuit block, the second circuit block
Is connected to the second macro circuit via the first switching circuit.
Connected to the first macro circuit side terminal of the
The terminal on the macro circuit side is connected between the macro circuits and the second terminal.
Connected to the second test mode terminal via the switching circuit.
It is characterized by being made to be.

[0021]

[0022]

When the first circuit block is tested alone, the first
The terminal on the second macro circuit side of the macro circuit is between the macro circuits.
The first test mode is connected via the connection and the first switching circuit.
To the first circuit block.
By performing simple tests click, it allows testing the connection state of macro circuits between connection.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to one embodiment of the present invention. In the figure,
The semiconductor integrated circuit 1 includes macro circuits 2 and 8, and a test mode control circuit 14. Macro circuit 2
Circuit block 3 for realizing functions, switching circuit 4
7, macro circuit signal input terminals 19 to 22, macro circuit signal output terminals 23 to 26, normal mode output terminals 29 to 3
2. It is composed of test mode terminals 49 to 52.
The switching circuits 4 to 7 switch the connection relationship between each of the above-described output terminals and the test mode terminal according to the control signal output from the test mode control circuit 14 to the control signal line 57 (change of mode setting).

The macro circuit 8 also includes a circuit block 9 for realizing functions, switching circuits 10 to 13,
It comprises normal mode input terminals 33 to 36, macro circuit signal input terminals 37 to 40, macro circuit signal output terminals 41 to 44, and test mode terminals 53 to 56. The switching circuits 10 to 13 are controlled by the control signal output from the test mode control circuit 14 to the control signal line 58.
The connection relation between the above-mentioned input terminals and the test mode terminals is switched.

The normal mode output terminals 29 to 32 of the macro circuit 2 are connected to the normal mode input terminals 33 to
36 are internally connected. The macro circuit signal input terminals 19 to 22 of the macro circuit 2 are connected to the external terminals 15 to 18 of the semiconductor integrated circuit 1, respectively, and the macro circuit signal output terminals 41 to 44 of the macro circuit 8 are connected to the outside of the semiconductor integrated circuit 1. They are connected to terminals 45 to 48, respectively. The control circuit 14 has a test mode control terminal 27,
It is controlled by a control signal input from the control signal.

Next, the operation of the semiconductor integrated circuit 1 of this embodiment shown in FIG. 1 will be described. In the normal operation mode, first, the test mode control circuit 14 is set to the normal operation state by a control signal for setting the normal operation state input from the test mode control terminals 27 and 28. As a result, the test mode control circuit 14 outputs a control signal for setting the normal operation mode to the control signal lines 57 and 58. By receiving the control signals output to the control signal lines 57, 58, the circuit blocks 3, 9 constituting the macro circuits 2, 8 are both set to the normal operation mode.

Further, in the switching circuits 4 to 7 receiving the control signal output to the control signal line 57, the macro circuit signal output terminals 23 to 26 are connected to the normal mode output terminals 29 to 32 of the macro circuit 2. Is controlled. Similarly, the switching circuits 10 to 13 are controlled so that the normal mode input terminals 33 to 36 of the macro circuit 8 are connected to the macro circuit signal input terminals 37 to 40. As a result, the macro circuit signal output terminals 23 to 26 of the macro circuit 2 are internally connected to the macro circuit signal input terminals 37 to 40 of the macro circuit 8 via the switching circuits 4 to 7 and the switching circuits 10 to 13, respectively. Will be. Then, in this state, the function is performed as a whole in the normal operation mode.

Next, the operation of each of the macro circuits 2 and 8 in the separation test mode will be described. First, when performing the isolation test of the macro circuit 2, the test mode control circuit 1
In the switching circuits 4 to 7 in the macro circuit 2, the switching signals 4 to 7 in the macro circuit 2 output the macro circuit signal output terminals 23 to 23 in the same manner as in the normal operation mode. 26 and macro circuit 2
Is controlled so as to be connected to the normal mode output terminals 29 to 32. On the other hand, the switching circuit 10 inside the macro circuit 8
13 to 13, the macro circuit 8 is controlled by the control signal output from the test mode control circuit 14 to the control signal line 58.
Of the normal mode input terminals 33 to 36 are the test mode terminals 5
It is controlled to connect to 3 to 56, respectively.

In the above test mode, the external terminal 1
By inputting the test pattern signals of the macro circuit 2 to 5 to 18 and observing the output signals from the test mode terminals 53 to 56, the function of the macro circuit 2 alone can be tested from the outside. At this time, the output signal of the macro circuit 2 is output from the macro circuit signal output terminals 23 to 26 →
Switching circuits 4 to 7 of macro circuit 2 → Normal mode output terminals 29 to 32 of macro circuit 2 → Normal mode input terminals 33 to 36 of macro circuit 8 → Switching circuit 1 of macro circuit 8
It is output from the test mode terminals 53 to 56 via the paths 0 to 23. Therefore, the connection state between the normal mode output terminals 29 to 32 of the macro circuit 2 and the normal mode input terminals 33 to 36 of the macro circuit 8 is also tested.

Similarly, when the isolation test of the macro circuit 8 is performed, the test mode control circuit 14 controls the control signal line 57.
The switching circuits 4 to 7 in the macro circuit 2 control the test mode terminals 49 to 52 so that the test mode terminals 49 to 52 are connected to the normal mode output terminals 29 to 32 of the macro circuit. Is done. On the other hand, in the switching circuits 10 to 13 inside the macro circuit 8,
As in the normal operation mode, the control signal output from the test mode control circuit 14 to the control signal line 58
Control is performed so that the normal mode input terminals 33 to 36 of the macro circuit are connected to the macro circuit signal input terminals 37 to 40, respectively.

As a result, by inputting the test pattern signal of the macro circuit 8 to the test mode terminals 49 to 52, it is possible to cause the macro circuit 8 to perform a desired operation for the test. By observing the signals output from .about.48, the function of the macro circuit 8 alone can be tested from the outside. At this time,
The test pattern signal is supplied to the switching circuit 4 of the macro circuit 2.
7 → Normal mode output terminals 29-32 of macro circuit 2 →
Macro circuit signal input terminals 37 to 40 of macro circuit 8 via normal mode input terminals 33 to 36 of macro circuit 8
Respectively.

Therefore, even in the separation test of the macro circuit 8, the test pattern signal passes from the normal mode output terminals 29 to 32 of the macro circuit 2 to the normal mode input terminals 33 to 36 of the macro circuit 8. This also tests the connection between the circuit 2 and the macro circuit 8.
As described above, according to this embodiment, when performing a separation test for each of the built-in macro circuits, a test is performed by inputting and outputting signals via internal macro circuit interconnections. This eliminates the need for a system test, which is a test of interconnection between built-in macro circuits.

Embodiment 2 FIG. FIG. 2 is a block diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention. In the figure, the same parts as those in FIG. 1 are denoted by the same reference numerals, and the detailed description is omitted below. 2, the semiconductor integrated circuit 1 includes macro circuits 2, 8 and a macro circuit 169.

In the normal operation mode, the mode of the test mode control circuit 14 is set by control signals from the test mode control terminals 27 and 28. Then, the control signals for the normal operation mode output to the control signal lines 57, 58, 164 from the macro circuits 2, 8, 169
Are all set to the normal operation mode. Further, switching circuits 4 to 7, 1
56 and 157, the macro circuit signal output terminal 23
~ 26,154,155 and normal mode output terminals 29 ~ 3
2, 160, 161 and the switching circuits 10 to 13 are controlled to connect the macro circuit signal input terminals 37 to 40 and the normal mode input terminals 33 to 36.

As a result, in the normal operation mode, first, the macro circuit signal output terminals 23 to 26 of the macro circuit 2 are internally connected to the macro circuit signal input terminals 37 to 40 of the macro circuit 8, respectively. The macro circuit signal output terminals 154 and 155 of the macro circuit 2 are connected to the macro circuit 1
The internal circuits are internally connected to the 69 macro circuit signal input terminals 167 and 168, respectively, and function as a normal operation mode as a whole.

Next, the respective macro circuits 2, 8, 16
9 will be described. First, when the isolation test of the macro circuit 2 is performed, the test mode control circuit 14 outputs to the control signal lines 57, 58, 164
According to the control signal used as the separation test, the switching circuits 4 to 7, 156, and 157 inside the macro circuit 2
As in the normal operation mode, control is performed so that the macro circuit signal output terminals 23 to 26, 154, and 155 are connected to the normal mode output terminals 29 to 32, 160, and 161 of the macro circuit.

In the switching circuits 10 to 13 in the macro circuit 8, the normal mode input terminals 33 to 36 of the macro circuit are tested by the control signal output from the test mode control circuit 14 to the control signal line 58, respectively. It is controlled to connect to the mode terminals 53 to 56, respectively. The switching circuit 1 inside the macro circuit 169
65 and 166 are controlled by the control signal output from the test mode control circuit 14 to the control signal 164 so that the normal mode input terminals 162 and 163 of the macro circuit are connected to the test mode terminals 175 and 176, respectively.

In this state, first, the external terminals 15 to 18,
Test pattern signals for testing the macro circuit 2 are input to 150 and 151. Then, by observing the output signal of the macro circuit 2 obtained as described above as an output signal obtained from the test mode terminals 53 to 56, 175, and 176 via the following path, the macro circuit 2 alone is externally observed. Function can be tested.

The above-mentioned path means that the macro circuit signal output terminals 23 to 26 → the switching circuit 4 to macro circuit 2
7 → Normal mode output terminals 29-32 of macro circuit 2 → Normal mode input terminals 33-36 of macro circuit 8 → Switching circuits 10-13 of macro circuit 8 → Test mode terminal 53
~ 56. Then, the macro circuit signal output terminal 15
4,155 → Switching circuits 156,15 of macro circuit 2
7 → Normal mode output terminals 160 and 161 of macro circuit 2
→ Normal mode input terminals 162, 16 of macro circuit 169
3 → Switching circuits 165, 166 of macro circuit 169 →
This is a path of the test mode terminals 175 and 176.

Similarly, when a separation test of the macro circuit 8 is performed, the test mode terminals 49 to 52 are used to output the macro circuit 8.
By inputting the test pattern signal and observing the operation state of the macro circuit 8 from signals output from the macro circuit external terminals 45 to 48, the function of the macro circuit 8 alone can be tested from the outside. Further, similarly, in the case where the separation test of the macro circuit 169 is performed, the test pattern signal of the macro circuit 169 is input from the test mode terminals 158 and 159, and the operation state of the macro circuit 169 is changed from the macro circuit external terminals 173 and 174. By observing the output signal, the macro circuit 16
9 can test the function of a single unit.

By performing the isolation test as described above, for example, when the isolation test of the macro circuit 2 is performed, the signal output from the macro circuit 2 in response to the input of the test pattern signal is output to the normal mode output terminal 29 of the macro circuit 2. .About.32 → the normal mode input terminals 33 to 36 of the macro circuit 8 and the normal mode output terminals 160 and 161 of the macro circuit 2 → the normal mode input terminals 162 and 163 of the macro circuit 169. Therefore, by performing the isolation test,
This also tests the connection state between the macro circuits, and does not require a separate system test.

Embodiment 3 FIG. In the above-described embodiment, the state in which two macro circuits are connected in series has been described. However, the present invention is not limited to this, and three or more macro circuits may be connected in series as shown in FIG. good. In the figure,
The macro circuit 181 has a circuit block 182, and signals are input to the macro circuit 181 from external terminals 15 to 18 via macro circuit signal input terminals 183 to 186.
Also, the macro circuit signal input terminals 19 to 22 of the macro circuit 2 via the macro circuit signal output terminals 187 to 190.
Connected to

The switching circuit may not be arranged in the macro circuit 181. 23a-
Reference numeral 26a denotes a macro circuit signal input terminal, and other reference numerals are the same as those in FIG. In the separation test mode of the macro circuit 181, the switching circuits 4 to 7 of the macro circuit 2 are switched to connect the macro circuit signal input terminals 19 to 22 and the test mode terminals 49 to 52.

As a result, the test pattern signal of the macro circuit 181 input from the external terminals 15 to 18 is input to the circuit block 182, and this circuit block 182
Are output from the test mode terminals 49 to 52 without being input to the circuit block 3 of the macro circuit 2. As a result, the separation test of the macro circuit 181 is performed, and the connection state between the macro circuit 181 and the macro circuit 2 is also tested. Thus, similarly to the above-described embodiment, it is not necessary to separately perform a system test. .

[0045]

As described above, according to the present invention, the first circuit block having the first circuit block having the macro function is incorporated.
One macro circuit and a second circuit block having a macro function.
And a second macro circuit with a built-in
In a standard cell type semiconductor integrated circuit connected to each other through the second macro circuit of the first macro circuit,
Connecting the roadside terminal to the terminal of the second circuit block,
Directly outside without connecting to the terminal of the second circuit block
First to switch connection to first test mode terminal
Switching circuit is connected between the macro circuit and the second circuit block.
Provided between the click of the terminal, the second macro circuit side terminal of the first macro circuit during a single test of the first circuit block
Is connected via the macro circuit connection and the first switching circuit.
1 test mode terminal . As a result, when a function isolation test is performed on one macro circuit, a signal can be input from an external terminal through an interconnection for connection with the other macro circuit to be connected. Can be tested at the same time. As a result, the system test (interconnection test between the built-in macro circuits) that has been required conventionally can be performed simultaneously with the macro separation test, so that this system test becomes unnecessary.

Therefore, the test time can be greatly reduced as compared with the related art, and the product cost can be further reduced. In addition, since a system test is unnecessary, a complicated and huge system test pattern for setting all states is not required in a state where a plurality of macro circuits are interconnected as in the related art. The time for creation can be greatly reduced, and the period for product development can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a semiconductor integrated circuit composed of two macro circuits.

FIG. 5 is a block diagram showing a configuration of a conventional semiconductor integrated circuit incorporating a macro separation test circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit, 2, 8 ... Macro circuit, 3, 9 ... Circuit block, 4-7, 10-13 ... Switching circuit, 14
... test mode control circuit, 15 to 18 ... external terminals, 19
~ 22,37 ~ 40 Macro circuit signal input terminal, 23 ~
26, 41-44... Macro circuit signal output terminals, 27, 2
8: Test mode control terminal, 29 to 32: Normal mode output terminal, 33 to 36: Normal mode input terminal, 49 to 56
... test mode terminals, 57, 58 ... control signal lines.

Claims (2)

(57) [Claims] 1. A first macro circuit having a first circuit block having a macro function and a second macro circuit having a second circuit block having a macro function are connected via a connection between the macro circuits. In a mutually connected standard cell type semiconductor integrated circuit, a terminal on the second macro circuit side of the first macro circuit is connected to a terminal of the second circuit block, or the second circuit block A first switching circuit for switching whether to directly connect to an external first test mode terminal without connecting to the second terminal.
A within the macro circuit, and, provided between terminals of the said macro-circuit between the connection the second circuit block, said first
When a single circuit block is tested, a terminal on the second macro circuit side of the first macro circuit is connected to the first test mode terminal via the inter-macro circuit connection and the first switching circuit. A semiconductor integrated circuit characterized in that: 2. A first circuit block having a macro function.
A built-in first macro circuit and a second macro circuit having a macro function
The second macro circuit with a built-in circuit block
Standard cells connected to each other via road-to-road connections
Terminal of the first macro circuit on the side of the second macro circuit in the semiconductor integrated circuit of the formula
Is connected to a terminal of the second circuit block, or the second
1st terminal directly outside without connecting to the terminal of the circuit block
First switch to switch between connecting to the test mode terminal of
A switching circuit in the second macro circuit, and
Connection between the macro circuits and a terminal of the second circuit block
And a terminal on the first macro circuit side of the second macro circuit.
Is connected to a terminal of the first circuit block, or the first
Second terminal directly connected to the outside without connecting to the terminal of the circuit block
Switch to switch between connecting to the test mode terminal of
A switching circuit in the first macro circuit; and
Connection between the macro circuits and a terminal of the first circuit block
Between the first circuit block and the first circuit block.
The terminal of the circuit block is connected via the second switching circuit.
And an end of the first macro circuit on the side of the second macro circuit.
And the terminal on the second macro circuit side is connected to the
Via the connection between the macro circuits and the first switching circuit
And connected to the first test mode terminal,
When testing a single circuit block of the second circuit block,
The lock terminal is connected to the second switching circuit via the first switching circuit.
2 macro circuit connected to the terminal on the first macro circuit side
And the terminal on the first macro circuit side is connected to the macro.
B via the circuit connection and the second switching circuit
That it is connected to the second test mode terminal
Characteristic semiconductor integrated circuit.