JPH03252574A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To test respective circuit blocks in parallel in a short time by providing test signal inputs by respective circuit blocks, terminals for output from them, test mode selection switching circuits, and an input terminal for control signals to it. CONSTITUTION:In testing operation, the control signal is inputted from one of the terminals 7 and the switching circuits 15 and 16 for the respective circuit blocks are turned off and set. Then when a test pattern for each circuit block unit function test is inputted from a test input terminal 18 corresponding to the circuit block, the output signals of the circuit block are outputted from the corresponding output terminal 22 and an input/output common terminal 17 and compared with prepared expected values, thereby deciding whether or not each circuit block function is normal according to the comparison result.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit in which a plurality of circuit blocks each having independent functions, such as a microprocessor and peripheral circuits, are formed on one semiconductor chip.

Conventional technology In recent years, with the improvement of manufacturing technology for semiconductor integrated circuits, semiconductors (hereinafter referred to as ASICs) have been developed for specific applications in which multiple circuit blocks each having independent logic functions, such as a microprocessor and peripheral circuits, are formed on a single semiconductor chip. Complex integrated circuits such as microcomputers (called microcomputers) have begun to be developed.

In the case of complex integrated circuits such as the above-mentioned ASIC micrococomputer, all circuits constituting one system are formed on one semiconductor chip, which is a so-called system-on-chip configuration, so as the scale of the system expands, the semiconductor The number of circuit blocks for each function on the chip will also increase significantly.

Conventionally, in testing the above-mentioned ASIC microcomputer, one circuit block is tested by setting each input terminal and output terminal of all the circuit blocks except one of the plurality of circuit blocks to a high impedance state. By separating the circuit blocks from other circuit blocks, the functionality of each circuit block was tested individually.

Problems to be Solved by the Invention However, if one of the plurality of circuit blocks is separated from the other circuit blocks and each circuit block is tested individually as in the conventional example described above, as the scale increases, As the number of circuit blocks constituting an ASIC microcomputer increases, there is a problem in that testing time increases accordingly.

Furthermore, as the number of circuit blocks increases, the length of each circuit block's des-l-pattern also increases, and furthermore, as the functions become more complex, it becomes difficult to separate the circuit blocks, so testing is becoming increasingly difficult from these points of view. It will be accompanied.

Other integrated circuit testing methods include boundary scan and BIST, which automatically tests the functionality of circuit blocks using a test mechanism built into the integrated circuit.
There are also methods (utilt in 5elf Te5t), but these methods are not effective in cases where a long test pattern is required to test each individual circuit block, such as the ASIC microcomputer mentioned above, and they increase the test time. I will invite you.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor integrated circuit that allows functional tests of individual circuit blocks formed on one semiconductor chip to be easily and quickly performed.

Means for Solving the Problems The present invention provides a semiconductor integrated circuit in which a plurality of circuit blocks each having independent functions are formed on a single semiconductor chip. a test input terminal for inputting a test signal; a test output terminal for taking out an output signal output from the circuit block to the outside of the semiconductor integrated circuit for each circuit block in accordance with a test signal input during a test operation; A switching circuit for selectively switching and setting signal lines that connect each circuit block and transmitting and receiving signals between them to a test mode state in which they are electrically disconnected; A semiconductor integrated circuit characterized in that a control signal input terminal for inputting a control signal for setting a test mode state to a switching circuit is provided from the input terminal to the switching circuit, so that each circuit block can be tested in parallel. be.

According to the present invention, the circuit blocks are separated from each other by the switching setting of the switching circuit based on the control signal input from the control signal input terminal, and the test signal input from the test input terminal for each circuit block is isolated from each other. The output signal outputted from each circuit block in accordance with the output signal is outputted to the outside from a test output terminal associated with each circuit block.

Therefore, the functional test of each circuit block can be performed in parallel.

Embodiment FIG. 2 is a block diagram showing a schematic configuration of a semiconductor integrated circuit to which an embodiment of the present invention is applied.

That is, this semiconductor integrated circuit consists of one semiconductor chip 2.
Above is the central processing unit W.
ng Unit (hereinafter abbreviated as CPU) 3 and a plurality of peripheral circuits 4a to 4d.
Input terminal 5 that provides input signals to individual circuit blocks of PLI 3 and each peripheral circuit 4a to 4d, data input terminal 6 that provides data to these circuit blocks, control signal input terminal 7 that provides control signals, and output from each circuit block. An address output field 8 takes out the address signal output from the semiconductor chip 2, and an address output field 8 takes out the address signal output from the semiconductor chip 2.
Output terminals 9 to be taken out to the outside are provided respectively.

Moreover, input signals are provided between each circuit block of the CPU 3 and peripheral circuits 4a to 4d! 10, an address signal line 11, a data bus 12, and other signal lines 13.

FIG. 1 is a circuit diagram showing an embodiment of a circuit configuration around one of the circuit blocks, for example, a peripheral circuit 4d, when the present invention is applied to the ASIC microcomputer.

A switching circuit n15 consisting of a tri-state buffer is inserted in the middle of the input terminal side signal line 14 of the peripheral circuit 4d, which is connected to the output terminal OUT of another circuit block.
An input terminal 15a of this switching circuit 15 is connected to an input/output common terminal 17 provided outside the semiconductor chip 2 via a bidirectional buffer 16. This input/output common terminal 1
7 corresponds to the input terminal 5 in FIG.
During actual operation, input signals to be input to the peripheral circuit 4d are input from this input/output common terminal 17.

A separate semiconductor chip 2 is connected to the input terminal of the peripheral circuit 4d.
A test input terminal 18 provided externally is connected by a wired OR 19.

The other input terminals of the peripheral circuit 4d have substantially the same connection configuration. However, the input terminal 15a of the switching circuit 15 may not only be connected to the input/output common terminal 17, but may also be connected to a simple input terminal 5 as shown in FIG.

On the other hand, a switching circuit 21 made of a tri-state buffer is also inserted in a portion of the signal line 20 connecting the output terminal of the peripheral port B4d and the input terminal IN of another circuit block on the output terminal side of the peripheral circuit 4d.

Furthermore, the test output terminal 22 separately provided outside the semiconductor chip 2 is connected to the output terminal of the 2 peripheral circuit 4d, and the other output terminals of the 0 peripheral circuit 4d have almost the same connection configuration. ing. However, if the output terminal corresponds to the address signal line 11 or data bus 12 in FIG. 2, the output terminals that output the common output signal between each circuit block are used during actual operation. Connected to the OR games 1 to 24 via a common bus 23 such as the address signal line 11 and data bus 12,
The configuration is such that these common output signals are multiplexed by an OR gate 24. The common output signal multiplexed by the OR gate 24 is taken out from the input/output common terminal 17 to the outside of the semiconductor chip 2 via the bidirectional buffer 16.

That is, the input/output common terminal 17 is commonly used as an input terminal during actual operation and an output terminal during test operation.

The sub-group terminals of each of the switching circuits 15.21 are connected to one of the control signal input terminals 7 shown in FIG.
21 is turned on. That is, when the switching circuit j815.21 is in the on state, the circuit blocks are in a connected state, that is, in the actual operation mode, and conversely, when the switching circuit j815.21 is in the off state, the circuit blocks are separated from each other. The state is in test mode.

In the above description, one peripheral circuit 4d has been taken as an example, but the same applies to other circuit blocks. Note that, for example, if the output terminal of the peripheral circuit 4d is not connected to the input terminal IN of another circuit block but is directly connected to the external output terminal 9, the switching circuit 21 is not required to be inserted. The output terminal 9 in this case is shared by the actual operation mode and the test mode.

Next, for the ASIC microcomputer 1,
The procedure for performing a functional test of each circuit block and an outline of the test operation will be explained.

During the test operation, first the specified control signal input terminal 7
A control signal for setting the test mode is input from one of the test modes. This control signal is used at the switching time of each circuit block.
&15.21, thereby switching times &fi
15.21 is switched to the off state. That is,
The circuit blocks are separated from each other.

Under the above bad settings, that is, test mode settings,
A test pattern for performing a functional test of each circuit block is inputted through the test input terminal 18 associated with each circuit block. Accordingly, the output signal of each circuit block is taken out from the test output terminal 22 and the input/output common terminal 17 associated with each circuit block. The extracted output signal of each circuit block is compared with an expected value of an output signal prepared in advance, and the quality of the function of each circuit block is determined from the comparison result.

In this way, in the test operation described above, functional tests of each circuit block such as the CPU 3 and the peripheral ports 1Ir4a to 4d can be performed simultaneously and in parallel.

During actual operation, each switching circuit 15 is connected from the control signal input terminal 7.
．． By inputting a control signal that turns off the circuit blocks 21, the circuit blocks are switched to an actual operation mode in which the circuit blocks are connected to each other by signal lines.

Effects of the Invention As described above, according to the semiconductor integrated circuit of the present invention, the switching circuit is switched and controlled by the M group signal inputted from the control signal input terminal, and each circuit block is isolated from each other. The configuration is such that a test signal is input to each circuit block and the output signal output from each circuit block is output to the outside from the test output terminal associated with each circuit block. Functional tests can be performed in parallel, and even semiconductor integrated circuits with expanded functionality can be tested easily and in a short time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the main parts of a semiconductor integrated circuit which is an embodiment of the present invention, and FIG. 2 is a block diagram showing the schematic structure of an ASIC microcomputer to which the embodiment is applied. . DESCRIPTION OF SYMBOLS 1... ASIC microcomputer, 2... Semiconductor chip, 3... CPU, 4a-4d... Peripheral circuit, 7... Control signal input terminal, 1.5.21... Switching circuit, 17... Input/output common terminal, 18... Test input terminal, 22... Test output terminal Figure 1 Figure 2

Claims (1)

[Claims] In a semiconductor integrated circuit in which a plurality of circuit blocks each having independent functions are formed on one semiconductor chip, a method for inputting a test signal for each circuit block from outside the semiconductor integrated circuit during a test operation is provided. A test input terminal, a test output terminal for taking out the output signal output from the circuit block according to the test signal input during test operation to the outside of the semiconductor integrated circuit for each circuit block, and between each circuit block. A switching circuit that selectively switches and sets the signal line that connects the signal lines and sends and receives signals between them to an electrically disconnected test mode state, and a switching circuit that connects the signal line and sends and receives signals between them. What is claimed is: 1. A semiconductor integrated circuit comprising: a control signal input terminal for inputting a control signal for setting a state of a test mode;