JPH04147072A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To test functions of individual circuit blocks easily in a short time by setting a plurality of circuit blocks having the same function simultaneously in an enable state, applying the same test data and determining whether or not outputs of the respective blocks coincide with one another. CONSTITUTION:A semiconductor chip 1 has a plurality of circuits 3a to 3c having the same function. A selection circuit 7 can simultaneously select the circuits 3a to 3c by combinations of input signals from a test signal input terminal 9 at the time of testing and can supply data input from a test data input terminal 16 to the circuits 3a to 3c simultaneously. A determining circuit 10 determines whether or not outputs of these circuits 3a to 3c coincide with one another, and the result is output from a test output terminal 15. Thus the circuits 3a to 3c are simultaneously tested while the test is easy and test time can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit having a plurality of identical functional circuit blocks on one semiconductor chip.

Conventional technology In recent years, with the improvement of manufacturing technology for semiconductor integrated circuits, semiconductors (hereinafter referred to as ASICs) have been developed for specific applications in which multiple circuit blocks each having independent logic functions, such as a microprocessor and peripheral circuits, are formed on a single semiconductor chip. Complex integrated circuits such as microcomputers (called microcomputers) have begun to be developed.

In the case of a complex integrated circuit such as the above-mentioned ASIC microcomputer, all the circuits constituting one system are formed on one semiconductor chip, which is a so-called system-on-chip configuration.As the scale of the system increases, the number of semiconductor chips increases. The number of circuit blocks above will also increase significantly.

Conventionally, in functional tests of complex integrated circuits such as the above-mentioned ASIC microcomputers, individual circuit blocks have been electrically isolated and tests have been serially performed on a circuit block basis.

Problems to be Solved by the Invention However, when testing individual circuit blocks serially as described above, there is a problem in that as the number of circuit blocks constituting a complex integrated circuit increases as the scale increases, the test time increases accordingly. Has a point.

Furthermore, as the number of circuit blocks increases, the test pattern length of each circuit block also increases, and furthermore, as the functions become more complex, it becomes difficult to separate the circuit blocks, so testing becomes increasingly difficult from these perspectives. become.

Therefore, an object of the present invention is to facilitate functional testing of individual circuit blocks formed on one semiconductor chip.
Another object of the present invention is to provide a semiconductor integrated circuit that can be manufactured in a short time.

Means for Solving the Problems The present invention provides a semiconductor integrated circuit having a plurality of identical functional circuit blocks on one semiconductor chip. a circuit that simultaneously sets the functional circuit blocks to an operable state; a test input terminal that simultaneously inputs the same test data to the plurality of identical functional circuit blocks during test operation; and an output from the plurality of identical functional circuit blocks during test operation. A determination circuit that determines whether or not each signal is matched, and a test output terminal that outputs the determination result of the determination circuit to the outside of the semiconductor integrated circuit are provided, and the plurality of identical functional circuit blocks can be simultaneously tested. This is a semiconductor integrated circuit characterized by the following features:

According to the present invention, a plurality of identical functional circuit blocks are simultaneously set to an operable state by a test signal applied from outside the semiconductor integrated circuit, and each identical functional circuit block is set to an operable state by a test signal applied from outside the semiconductor integrated circuit. Test data is applied, and a determination circuit determines whether or not the outputs of the respective identical functional circuit blocks match, and the determination result is output from the test output terminal. As a result, a plurality of identical functional circuit blocks are functionally tested at the same time.

Embodiment FIG. 1 is a block diagram showing the basic configuration of a semiconductor integrated circuit which is a first embodiment of the present invention.

That is, this semiconductor integrated circuit consists of one semiconductor chip 1.
Above is a central processing unit (CentralProcessi).
ng Unit (hereinafter abbreviated as CPU) 2, a plurality of identical functional circuits 3a, 3b, 3c, and a logic circuit 4, all of which have the same function.

The above CPU2. The respective circuit blocks of the same functional circuits 3a to 3cm logic circuit 4 are interconnected via a data bus 5 and an address bus 6.

The selection circuit 7 provided separately from each of the circuit blocks described above is
It consists of a plurality of selectors 7a to 7C that correspond one-to-one to each of the same functional circuits 3a to 3C.
It has a function of individually selecting the same functional circuits 3a to 3C by a control signal given from 2.

The selection circuit 7 is also connected to a test signal input terminal 9 provided outside the semiconductor chip 1 via the same control bus 8, and receives signals input from the test signal input terminal 9 during test operation. It is also possible to select a plurality of the same functional circuits 3a to 3C at the same time by combining them.

Furthermore, the data bus 5 is also connected to a test data input terminal 16 provided outside the semiconductor chip 1, and the same test data inputted from the test data input terminal 16 during a test operation is transmitted to each of the same functional circuits 3a to 3C. It is configured so that it can be supplied at the same time.

The output terminals of each of the same function circuits 3a to 3C are connected to the input terminal of the other circuit to which the output is to be sent during actual operation, or to an output terminal provided outside the semiconductor chip 1, etc. It is also connected to an input terminal of the determination circuit 10.

The determination circuit 10 is a circuit for determining whether the outputs of the same function circuits 3a to 3c match or not during a test operation, and the output terminal for outputting the determination result is of the semiconductor chip 1. External test output terminal 1
5.

FIG. 2 shows each of the same function circuits 3a to 3c and the determination circuit 10.
FIG. 2 is a circuit diagram showing a connection configuration with.

The judgment circuit 10 has three exclusive OR gates 11 to 1.
It is composed of 4. Each same functional circuit 3a to 3c
have three output terminals, the first outputs al, bl, and cl of the same function circuits 3a to 3c are given as inputs to the exclusive OR gate 11, and the first outputs of the same function circuits 3a to 3C are 2 output a2. b2. c2 is exclusively given as an input to the OR gate 12, and is further supplied to the third outputs a3 . b3 c3 is given as an input to the exclusive OR gate 13, each output of the three exclusive OR gates 11 to 13 is given as an input to the remaining exclusive OR gate 14, and the exclusive OR gate 14 The configuration is such that the output is taken out from the test output terminal 15 as the determination result.

Next, a test operation of the same functional circuits 3a to 3c in the ASIC microcomputer will be described.

During the test operation of the same function circuits 3a to 3c, a predetermined combination of test signals is input from the test signal input terminal 9 to the selection circuit 7 via the control bus 8, whereby all the same function circuits 3a to 3c operate. Selected and set to possible state.

Under the above setting state, when test data is input from the test data input terminal 16, each of the same function circuits 3a to 3
c takes in the same test data and provides the corresponding output to the determination circuit 10.

Since the functions of the same function circuits 3a to 3c are the same, if these functions are normal, the corresponding outputs of the same function circuits 3a to 3c will match each other.

The exclusive OR gate 11 of the determination circuit 10 determines whether the first outputs al and blc1 of the same functional circuits 3a to 3C match or do not match, and if they match, the output of the exclusive OR gate 11 is Low level, high level in case of mismatch. Similarly, in the exclusive OR gate 12, the second outputs a2. b2. The exclusive OR gate 13 outputs the third outputs a3.c2 of the same function circuits 3a to 3c. b3. It is determined whether c3 matches or does not match. Further, the exclusive OR gate 14 determines whether the outputs of the three exclusive OR gates 11 to 13 match or not, and if the corresponding outputs of the same function circuits 3a to 3C all match, the The output A of the OR gate 14 becomes low level,
Otherwise, it will be at a high level. Therefore, by monitoring the output A of the exclusive OR gate 14 taken out from the test output terminal 15 with the test device,
Functional tests can be performed on all of the plurality of identical functional circuits 3a to 3c at the same time.

FIG. 3 is a circuit diagram showing the circuit configuration of a main part of a semiconductor integrated circuit according to a second embodiment of the present invention.

That is, the semiconductor integrated circuit of this embodiment is provided with a determination circuit 20 having the configuration shown in FIG. 3 in place of the determination circuit 10 of the first embodiment, and the other configuration is the same as that of the first embodiment. Same as in the example.

In addition to the circuit configuration part of the previous determination circuit 10, this determination circuit 20 includes an inverter 17 that inverts the output A obtained from the circuit configuration part, and a
Three AND gates 18 to 20 corresponding to the two outputs are added, and a signal B obtained by inverting the output A by an inverter 17 is applied as a single input to each AND gate 18 to 20. one, for example, each output al, a2 . of the same functional circuit 3a. a3 is provided as the other one power of each AND gate 18 to 20, respectively. The outputs of the AND gates 18 to 2O are connected to test output terminals 21 to 23 provided outside the semiconductor chip 1 in association with these AND gates, respectively.

In this embodiment, all the same functional circuits 3 are used in the test operation.
If the outputs of a to 3c match, output A as described above
may become a low level, so each A
The single-person power given to ND gates 18 to 20 is at a high level.

Therefore, at this time, each of the outputs al, a of the same functional circuits 3a to 3c which are operated by one person other than each AND gate 18 to 20
2. A3 is taken out from the ASIC microcomputer from the corresponding test output terminals 21 to 23 via the AND gates 18 to 20.

The same function circuit 3a at this time represents all the same function circuits 3a to 3c whose functions are normal, and monitoring the outputs a1 to a3 taken out from the test output terminals 21 to 23 is the same for all the same function circuits 3a to 3c. This is equivalent to monitoring the outputs of the functional circuits 3a to 3c.

Note that when the outputs of the same function circuits 3a to 3c do not match, the inverted signal B of the output A becomes low level, so the outputs a1 to a3 of the same function circuits 3a are taken out from the test output terminals 21 to 23. Not done. From this, it can be known that at least one of the same functional circuits 3a to 3C has an abnormal function.

FIG. 4 is a circuit diagram showing the circuit configuration of a main part of a semiconductor integrated circuit according to a third embodiment of the present invention.

That is, the semiconductor integrated circuit of this embodiment is provided with a determination circuit 30 having the configuration shown in FIG. 4 in place of the determination circuit 10 in the first embodiment, and the other configuration is the same as that of the first embodiment. The same is true for .

This determination circuit 30 is similar to the determination circuit 2 in the second embodiment.
0 AND gates 18-20 are replaced with D flip-flops 31-33, respectively. The rest of the configuration is the same as the determination circuit 20 in the second embodiment. That is, a signal B obtained by inverting the output A by the inverter 17 is given as a clock input to each D flip-flop 31 to 33, and each of the three outputs a1 to a of the same functional circuit 3a is
3 is given as a data input to each D flip-flop 131-33, and each D flip-flop 31-3
3 outputs are taken out from the corresponding test output terminals 21 to 23, respectively.

In this embodiment, all the same functional circuits 3 are used in the test operation.
If the outputs of a to 3c match, output A as described above
becomes low level, each D
Signal B applied as a clock input to flip-flops 31 to 33 is kept at a high level.

Therefore, at this time, each D flip-flop 31 to 33
Each output al, a of the same functional circuit 3a becomes the data input of
2. A3 is taken out from the ASIC microcomputer from the corresponding test output terminals 21 to 23 through each D flip roller 131 to 33.

It should be noted that when the signal B is inverted from high level to low level, that is, when a mismatch occurs between the outputs of the same function circuits 3a to 3c, at that point each D free-, 11 flop 31 to 33 is connected to the same function circuit. Each corresponding output a from 3a
1 to a3 are held, respectively, and the outputs taken out from the test output terminals 21 to 23 do not change thereafter. From this, it can be known that at least one of the same functional circuits 3a to 3c has an abnormal function.

FIG. 5 is a circuit diagram showing a connection configuration between each of the same functional circuits 3a to 3c and a determination circuit 40 of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

The determination circuit 40 in this embodiment includes the three exclusive OR gates 11 to 1 in the determination circuit 10 in the first embodiment.
D flip-flops 41a to 4 are provided at each input stage of 3.
3c, and the other configuration is the same as that of the determination circuit 10 of the first embodiment.

That is, the first output a1 of the same function circuit 3a is used as the data input of the D flip-flop 41a, the first output b1 of the same function circuit 3b is used as the data input of the D flip-flop 41b, and the first output b1 of the same function circuit 3b is used as the data input of the D flip-flop 41b. The output c1 of is given as the data input of each D flip-flop 41c, and these three D flip-flops 41a to 4
Each output of 1c is given as three outputs of exclusive OR gate 11. In addition, each of the above-mentioned D flip-flops 41a~
The same synchronizing signal T1 is applied to 41c as a clock input. As this synchronization signal T1, for example, this AS
The system clock used during actual operation of the IC microcomputer is shared.

Similarly, the second output a2~ of each of the same functional circuits 3a~3c
c2 is the data input of the D flip-flops 42a to 42C, and the third output a3 to each of the same function circuits 3a to 3C.
c3 is given as a data input to each of the D flip-flops 43a to 43c, and the D flip-flop 42
The respective outputs of the D flip-flops 43a to 43c are provided as the three outputs of the exclusive OR gate 12, and the outputs of the D flip-flops 43a to 43c are respectively provided as the three inputs of the exclusive OR gate 13. Further, the same synchronizing signal T2 is applied as a clock input to the D flip-flops 42a to 42c, and the same synchronizing signal T3 is applied as a data input to the D flip-flops 43a to 43C from outside the ASIC microcomputer.

FIG. 6 is a timing chart showing the latch operations of the D flip-flops 41a to 41c in the determination circuit 40.

In this embodiment, in the test operation, the same output, for example, output al, of each of the same functional circuits 3a to 3c.

When there is a shift in the inversion timing of bl and cl as shown in Fig. 6, the states of the respective outputs al, bl, and cl are changed by the synchronization signal T1 shown in Fig. 6 (4) given from outside the ASIC microcomputer. Perfect timing t
1 and these outputs correspond to the D flip-flop 41a.
~41c, and each of the held outputs a1 to c1 is given as a triple output of the corresponding exclusive OR gate 11.

The second output and third output of each of the same function circuits 3a to 3c are also D flip-flops 42a to 42c, 43a to
43c under the same state timing, and is given as each three inputs of the corresponding exclusive OR gates 12 and 13. The processing by the exclusive OR gates 11 to 14 is the same as in the first embodiment.

As described above, in each embodiment, a plurality of identical functional circuits 3
For the functional tests a to 3c, it is sufficient to prepare only one test output terminal of the same functional circuit.

Effects of the Invention As described above, according to the semiconductor integrated circuit of the present invention, a plurality of identical functional circuit blocks can be simultaneously set to an operable state by a test signal applied from outside the semiconductor integrated circuit,
The same test data is applied to each of the same functional circuit blocks from the test input terminal, the judgment circuit judges whether the outputs of the same functional circuit blocks match or not, and the judgment result is taken out from the test output terminal. Since the integrated circuit is configured as Blocks can be tested simultaneously, making testing easier and significantly reducing testing time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of a semiconductor integrated circuit which is a first embodiment of the present invention, FIG. 2 is a circuit diagram showing the circuit configuration of the main part of the semiconductor integrated circuit, and FIG. FIG. 4 is a circuit diagram showing the circuit configuration of the main part of a semiconductor integrated circuit according to the second embodiment of the invention, and FIG. 4 is a circuit diagram showing the circuit structure of the main part of the semiconductor integrated circuit according to the third embodiment of the invention. , FIG. 5 is a circuit diagram showing the main circuit configuration of a semiconductor integrated circuit according to a fourth embodiment of the present invention, and FIG. 6 is a timing chart showing the operation of the determination circuit in the semiconductor integrated circuit. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 3a-3c... Same function circuit, 5... Data bus, 7... Selection circuit, 8... Control bus, 9... Test signal input terminal, 10, 20, 30
．． 40... Judgment circuit, 15... Test output terminal, 1
6...Test data input terminal agent Patent attorney Number of strokes Keiichi No. 1

Claims (1)

[Claims] In a semiconductor integrated circuit having a plurality of identical functional circuit blocks on one semiconductor chip, the plurality of identical functional circuit blocks are simultaneously operated by a test signal input from outside the semiconductor integrated circuit during a test operation. A circuit to be set to an operable state, a test input terminal for simultaneously inputting the same test data to the plurality of identical functional circuit blocks during test operation, and each signal output from the plurality of identical functional circuit blocks during test operation. A determination circuit for determining whether or not they match, and a test output terminal for outputting the determination result of the determination circuit to the outside of the semiconductor integrated circuit are provided, and the plurality of identical functional circuit blocks are simultaneously tested. A semiconductor integrated circuit characterized by: