JP2672408B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a microprocessor,
The present invention relates to a semiconductor integrated circuit in which a plurality of circuit blocks each having an independent function such as a peripheral circuit are formed on one semiconductor chip.

[0002]

2. Description of the Related Art In recent years, with the improvement of manufacturing technology of semiconductor integrated circuits, application-specific integrated circuits (hereinafter referred to as ASICs) in which circuit blocks having independent logical functions such as microprocessors and peripheral circuits are formed on one semiconductor chip. Called)) is being developed.

A method called a mega cell method is used for designing the above-mentioned ASIC. The mega cell referred to here is one in which a plurality of basic circuit blocks, that is, basic cells, are combined into one circuit block having a predetermined function. In this mega cell system, an LSI having a desired function by using one or more of the above mega cells
(Large Scale Integrated circuit)
Is designed.

FIG. 4 shows an L designed by the above megacell system.
FIG. 2 is a block diagram schematically showing the configuration of SI on a semiconductor chip 1, in which three mega cells 2a, 2b, 2c are shown.
The LSI is composed of.

LS designed by such a megacell system
In the case of I, not only is the function of each megacell complicated, but the connection between individual megacells is also connected to each other by a signal line, which makes the test extremely difficult when the entire chip is tested at once. Is becoming.

Therefore, conventionally, in such an LSI test, a method of performing a test for each individual megacell has been adopted. As one of the test methods, there is a method in which a program having an instruction to control a megacell is used to set only one megacell to be tested in an operating state and all other megacells are in a non-operating state to perform a test. Are known.

FIG. 5 shows L used to explain the test method.
FIG. 6 is a block diagram showing a schematic configuration of SI, and FIG.
It is a timing chart which shows the procedure of the test method. In FIG. 5, an LSI is composed of a CPU core 3 in which only the CPU portion of the microprocessor is a mega cell and a DMA cell 4 which is a mega cell having a direct memory access function.

Next, the outline of the test method will be described with reference to FIGS. 5 and 6. Here, the CPU core 3 is tested first, and then the DMA cell 4 is tested.

First, in the test period (t0 to t1),
The DMA cell 4 is put into a non-operating state. The procedure is as follows. In the test program which gives an instruction from the test address buses A0 to A15 to each of the megacells 3 and 4, the CPU core 3 sends the data bus D0 to D7 as the first instruction.
Through, prepares an instruction to send data to the DMA cell 4 to put the DMA cell 4 into an inactive state. When the CPU core 3 executes this instruction, the DMA cell 4
Becomes inactive.

During the next test period (t1 to t2), C
The PU core 3 is tested.

When the test is completed, the CPU core 3 is deactivated in the next test period (t2 to t3),
In addition, the DMA cell 4 is put into operation. The procedure is as follows. The CPU core 3 is set to the BUSRQ enabled state by an instruction from the test address buses A0 to A15. Then, from the CPU core 3 to the data buses D0 to D7
Via the bus request communication line BUSRQ to the DMA cell 4 via the bus request communication line BUSRQ. As a result, the CPU core 3 receives the BUSRQ from the DMA cell 4, and the CP
The U core 3 is in a non-operating state.

During the next test period (t3 to t4), D
The MA cell 4 is tested. In this way, each megacell 3, 4 can be tested individually.

In the above-mentioned test method, the state of the registers and flip-flops of the test-target megacell and the non-test-target megacell changes due to the processing for setting the non-test-target megacell to the non-operating state. In order to avoid this, another test method shown below has been conventionally used.

FIG. 7 is a block diagram schematically showing the structure of an LSI to which the other test method is adopted. Each of the megacells 5a and 5b has a test signal line 6ai,
6ao, 6bi and 6bo are connected, and these test signal lines are connected to connection circuits 7ai, 7ao and 7b, respectively.
The test common signal lines 8i and 8o are connected via i and 7bo, and the test common signal lines 8i and 8o are connected to the corresponding test input terminals 9i and 9o, respectively.

Among the test signal lines, the test setting terminals 11a are connected to the connecting circuits 7ai and 7ao corresponding to the test signal lines 6ai and 6ao of the megacell 5a through the test setting signal line 10a. Of the test signal lines, test signal lines 6bi and 6bo of the megacell 5b
A test setting terminal 11b is connected to the connecting circuits 7bi and 7bo corresponding to the above-mentioned circuit via a test setting signal line 10b.

The test method in this case will be described below with reference to FIG. Here, the case where the mega cell 5a is the test target and the mega cell 5b is excluded from the test target is shown. Each of the connection circuits 7ai, 7ao, 7bi, 7bo makes the corresponding test signal line a corresponding test common signal line when the test setting signals TA, TB input from the corresponding test setting terminals 11a, 11b are at a high level. connection,
When the test setting signals TA and TB are at a low level, the test common signal line is disconnected.

Now, when the test setting signal TA is set to the high level, the connection circuits 7ai and 7a corresponding to the mega cell 5a are formed.
o connects the test signal lines 6ai and 6ao to the corresponding test common signal lines 8i and 8o, respectively.

At this time, the test data input from the test input terminal 9i is the mega cell 5a via the test common communication line 8i, the connection circuit 7ai, and the test signal line 6ai.
The signal input to and output from the megacell 5a is
It is led to the test output terminal 9o through the test signal line 6ao, the connection circuit 7ao, and the test common signal line 8o.
Therefore, the operation of the mega cell 5a according to the test data can be evaluated outside the semiconductor chip.

The other mega cells 5b can be independently tested by the same procedure.

[0020]

In the conventional semiconductor integrated circuit shown in FIG. 7, the megacells can be individually tested without changing the internal state of each megacell, but the number of megacells 5a and 5b is increased. Since the test setting terminals 11a and 11b corresponding to the above are required, the number of pins of the package increases as the number of mega cells increases.

Therefore, an object of the present invention is to provide a semiconductor integrated circuit which can be tested for each circuit block without changing the internal state and without increasing the number of pins of the package.

[0022]

According to the present invention, in a semiconductor integrated circuit in which a plurality of circuit blocks each having an independent function are formed on one semiconductor chip, a test is performed between each of the circuit blocks and the outside of the semiconductor chip. A test signal line common to each circuit block that inputs and outputs signals and a normal signal line used for inputting and outputting signals of each circuit block during actual operation are provided in association with each other. Connection switching circuit for selectively connecting a signal line for a circuit to a circuit block, and a circuit block designating test signal which is provided in association with each of the circuit blocks and is input from outside the semiconductor chip through the test signal line. receive,
When the test signal designates the corresponding circuit block, the connection switching circuit corresponding to the circuit block is switched from the state in which the normal signal line is connected to the circuit block to the state in which the test signal line is connected. When the circuit block designating test signal does not designate the corresponding circuit block, the connection switching circuit corresponding to the circuit block is disconnected from the circuit block by both the normal signal line and the test signal line. And a test detection circuit for controlling switching to a selected state.

[0023]

According to the present invention, when a test signal designating one circuit block is input from outside the semiconductor chip through the test signal line, the test detection circuit corresponding to the designated circuit block corresponds to that circuit block. The connection switching circuit is switched from the state in which the normal signal line is connected to the circuit block to the state in which the test signal line is connected to the circuit block, and the test detection circuits corresponding to other circuit blocks that are not designated are The connection switching circuit corresponding to the circuit block is switched to a state in which both the normal signal line and the test signal line are disconnected from the circuit block. As a result, the test signal line is connected only to the designated circuit block, and the individual test of the designated circuit block can be performed through the test signal line.

[0024]

1 is a block diagram showing a schematic structure of a main portion of a semiconductor integrated circuit according to an embodiment of the present invention. This semiconductor integrated circuit is an LSI configured by forming a plurality of mega cells on one semiconductor chip 12, and only one mega cell 13 among them is shown in FIG.

The megacell test circuit 30 is a circuit for setting only one arbitrary megacell 13 into a testable connection state, and is provided in a one-to-one correspondence with each megacell 13.

The megacell test circuit 30 includes the input / output units I / O-1, I / O-2, ..., I / O of the megacell 13.
ON to N are used as a normal line 14 and a test data bus line 15D0, 15D1, ..., 15D7 used in actual operation.
16-N (hereinafter, referred to as a general connection switching circuit in general). When indicated, it is indicated by reference numeral 16) and a test signal for mega cell designation given from the outside of the semiconductor chip 12 through the test data bus 15
It is composed of a test detection circuit 17 for controlling the switching state of the connection switching circuit 16.

A test mode signal line 18 is connected to the test detection circuit 17. The test mode signal line 18 and the test data bus 15 are connected to terminals 19 and 20 outside the semiconductor chip 12, respectively.

FIG. 2 is a circuit diagram showing a specific configuration of the connection switching circuit 16 and the test detection circuit 17.
The test detection circuit 17 includes a megacell number match determination circuit 21.
, A NOR gate 22 and an AND gate 23.

The megacell number coincidence determination circuit 21 receives the semiconductor chip 12 through the test data bus line 15.
This is a circuit for determining whether or not the mega cell number included in the mega cell designating test signal given from the outside matches the mega cell number previously assigned to the corresponding mega cell 13.

The output of the mega cell number coincidence judging circuit 21 and the mode designating signal inputted from the outside of the semiconductor chip 12 to the test detecting circuit 17 through the test mode signal line 18 are given as two inputs of the NOR gate 22, The output is sent to the connection switching circuit 16 as the first connection switching signal S1.

The AND gate 23 is also supplied with the output of the megacell number coincidence judging circuit 21 and the mode designating signal as two inputs, and the output of the AND gate 23 is the second connection switching signal S2 as the connection switching circuit 16 Sent to.

Each connection switching circuit 16 has two inputs 3
It is composed of state gates 24a and 24b and two output 3-state gates 25a and 25b. One input 3-state gate 24a is interposed between one input of the megacell 13 and one of the normal lines 14, and the other one input 3-state gate 24b is tested with the same input of the megacell 13. It is inserted between one of the data bus lines 19 for use.

Further, one output 3-state gate 25
a is one output of the mega cell 13 and one of the normal lines 14.
The other output 3-state gate 25b is inserted between the same output section of the mega cell 13 and one of the test data bus lines 19.

The connection switching signal S1 from the NOR gate 22 in the test detection circuit 17 is given as a control signal for the input 3-state gate 24a and the output 3-state gate 25a. In addition, the test detection circuit 17
Connection switching signal S2 from the AND gate 23 in
Is the input 3-state gate 24b and the output 3-state gate 24b.
It is given as a control signal for the state gate 25b.

FIG. 3 shows the megacell number matching judgment circuit 2 described above.
It is a circuit diagram which shows the specific structure of 1. Here, EX-N of the number corresponding to the number of test data buses 15 is used.
OR gates 26 _{0 to} 26 ₇ (hereinafter denoted by reference numeral 26 when representing an EX-NOR gate in general) and an AND gate 2
7 and a flip-flop 28.

Each EX-NOR gate 26 receives a test signal from one of the test data bus lines 15 and a high level (corresponding to "1" of the two values. The same applies hereinafter) or a low level (two values). Equivalent to "0" of the above.
And a signal for referring to the mega cell number which is set in advance to each of the two. Each EX-NOR gate 26
The mega cell number reference signal corresponding to is set to be binary data indicating the mega cell number assigned to the corresponding circuit block 13. That is, in the megacell number coincidence determination circuit 21, the megacell number assigned to the corresponding circuit block 13 is the EX-NOR gate 26.
Is set in advance as one input for each.

The output of each EX-NOR gate 26 is given as an input of the AND gate 27 of the next stage, and the output of the AND gate 27 is given as a data input of the flip-flop 28 of the next stage. Further, the test signal input through the test mode signal line 18 is the flip-flop 28.
, And the data output of the flip-flop 28 becomes the output of the megacell coincidence determination circuit 21.

Next, the operation of individually testing each megacell 13 of the above LSI will be described. At the time of a test, first, a high-level test signal designating a test mode is input from a terminal 20 outside the semiconductor chip 12, and a megacell designating test signal designating a circuit block 13 to be tested, that is, one megacell, from a terminal 19. Binary data representing a number is input.

These test signals are applied to the test detection circuit 17 of the megacell test circuit 14 associated with each circuit block 13 through the test data bus line 15 and the test mode signal line 18.

That is, in the mega cell number coincidence judging circuit 21 of the test detecting circuit 17, the mega cell designating test signal is applied as one input to each EX-NOR gate 26. When the megacell designating test signal, that is, the megacell number, coincides with the megacell number set as the other one input of the EX-NOR gate 26, all the EX-NOR gates 26 in the megacell number coincidence determination circuit 21. The output becomes high level, and the output of the AND gate 27 which receives these outputs is inverted from low level to high level. This output is given to the flip-flop 28.

Further, the test signal to the test mode signal line 18 designating the test mode is input to the flip-flop 28 as a clock signal, and the high level output from the AND gate 27 is output by the rising of the test signal. And the high-level output is taken out from the flip-flop 28 as the output of the megacell number coincidence determination circuit 21.

At this time, N in the test detection circuit 17
Since the two inputs of the OR gate 22 and the AND gate 23 both become high level, the output of the NOR gate 22, that is, the connection switching signal S1 becomes low level, and the output of the AND gate 23, that is, the connection switching signal S2 becomes low level.

Therefore, in the connection switching circuit 16 associated with the circuit block 13 having the same megacell number, the input 3-state gate 24a and the output 3-state gate 25a are switched off at a low level. The signal S1 is applied to the input 3-state gate 24b and the output 3-state gate 25.
A high level connection switching signal S2 for turning them on is applied to b.

As a result, in the circuit block 13, the input / output sections I / O-1, I / O-2, ..., I / O-N are separated from the corresponding normal line 14, and the test data bus line is provided. 15D0, 15D1, ..., 15D7 are connected.

On the other hand, when the mega cell number coincidence determination does not match, the output of the AND gate 27 in the mega cell number coincidence determination circuit 21 becomes low level, so that the output of the mega cell number coincidence determination circuit 21 also becomes low level. Further, since the test signal introduced to the test mode signal line 18 is at the high level designating the test mode, the connection switching signal S1 which is the output of the NOR gate 22 in the test detection circuit 17 is at the low level and the output of the AND gate 23. Also, the connection switching signal S2, which is, becomes low level.

That is, in all the remaining circuit blocks 13 whose mega cell numbers do not match, the input / output units I / O-1,
I / O-2, ..., I / O-N are the corresponding normal lines 14
From the test data bus lines 15D0, 15D1,
…, 15D7 is also kept separated.

The output of the mega cell coincidence judging circuit 21 continues to be latched by the flip-flop 28 unless the test signal introduced from the test mode signal line 18 is returned to the low level. Therefore, in this state, the input of the mega cell designating test signal is stopped. Will be maintained.

Under this condition, by inputting test data from any one of the terminals 19 outside the semiconductor chip 12 and taking out test response data from the other terminals 19,
The individual test of the circuit block 13 is performed.

That is, the input test data is the test data bus line 15 and the connection switching circuit 16.
Via the connection, the output data from the circuit block 13 which is input to only one circuit block 13 designated by the matching of the megacell numbers and which responds to it is connected to the connection switching circuit 16
And it is taken out of the semiconductor chip 12 through the test data bus line 15.

Under the above conditions, the test mode signal line 1
When the introduction of the test signal to 8 is stopped, that is, when the test signal is switched from the high level to the low level, the signal is input as a reset signal to the flip-flop 28 in the mega cell number coincidence determination circuit 21, and the mega cell number coincidence determination circuit 21. The output of returns to the original low level.

Therefore, in the test detection circuit 17 associated with all the circuit blocks 13, the connection switching signal S1 output from the NOR gate 22 is at a high level and the connection switching signal S2 output from the AND gate 23 is at a low level. Becomes

As a result, in all the circuit blocks 13, the input / output units I / O-1, I / O-2, ..., I / O-N.
Are test data bus lines 15D0, 15D1, ..., 15
It disconnects from D7 and returns to the normal connection state in which it is connected to the corresponding normal line 14.

Table 1 shows the correspondence between the combination of the judgment output of the megacell number coincidence judgment circuit 21 and the test mode setting test signal and the connection switching signals S1 and S2 in the above operation.

[0054]

[Table 1]

[0055]

As described above, according to the semiconductor integrated circuit of the present invention, a test signal for designating one circuit block is inputted from the outside of the semiconductor chip through the test signal line, and the connection corresponding to the designated circuit block is made. The test circuit corresponding to the same circuit block switches the switching circuit from the state where the normal signal line is connected to the circuit block to the state where the test signal line is connected, and the test corresponding to other circuit blocks not specified Since the detection switching circuit switches the connection switching circuits corresponding to those circuit blocks to the state in which both the normal signal line and the test signal line are disconnected from the circuit blocks, the semiconductor switching circuit is used in accordance with the increase in the number of circuit blocks. Test signal lines only for designated circuit blocks without increasing the number of pins outside the chip Under the state where the connection can be performed alone test circuit block.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit that is an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a test detection circuit and a connection switching circuit in the embodiment.

FIG. 3 is a circuit diagram showing a specific configuration of a megacell number matching determination circuit according to an embodiment.

FIG. 4 is a block diagram showing an example of an ASIC based on a mega cell system.

FIG. 5 is a block diagram showing an example of a semiconductor integrated circuit to which a conventional test method is applied.

FIG. 6 is a timing chart showing the procedure of a test method.

FIG. 7 is a block diagram showing an example of a semiconductor integrated circuit to which another conventional test method is applied.

[Explanation of symbols]

 12 semiconductor chip 13 circuit block 14 normal line 15 test data bus line 16 connection switching circuit 17 test detection circuit 18 test mode signal line

Claims (1)

(57) [Claims] 1. In a semiconductor integrated circuit in which a plurality of circuit blocks each having an independent function are formed on one semiconductor chip, each circuit for inputting / outputting a test signal between each of the circuit blocks and the outside of the semiconductor chip. A test signal line common to blocks and a normal signal line used for inputting / outputting signals of each circuit block during actual operation are provided in association with each other, and the normal signal line and the test signal line are selectively circuited. A connection switching circuit connected to a block and a circuit block designating test signal provided from the outside of the semiconductor chip via the test signal line provided in association with each circuit block, and the test signal corresponds. When the circuit block to be specified is specified, the connection switching circuit corresponding to the circuit block is connected to the normal signal line. When the switching control is performed from the state to the state in which the test signal line is connected, and the circuit block designating test signal does not designate the corresponding circuit block,
A semiconductor integrated circuit, comprising: a connection detecting circuit corresponding to the circuit block; and a test detecting circuit for controlling switching of the normal signal line and the test signal line so as to be separated from the circuit block. .