JP2709334B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in which a plurality of circuit blocks having independent functions such as a microprocessor and a peripheral circuit are formed on a single semiconductor chip.

2. Description of the Related Art In recent years, with the improvement in the manufacturing technology of semiconductor integrated circuits, application-specific semiconductors (hereinafter referred to as ASICs) in which a plurality of circuit blocks having independent logic functions such as a microprocessor and peripheral circuits are formed on a single semiconductor chip. Complex integrated circuits such as microcomputers) have been developed.

In the case of a complex integrated circuit such as the ASIC microcomputer described above, all the circuits constituting one system
Since a so-called system-on-chip configuration is formed on one semiconductor chip, the number of circuit blocks for each function on the semiconductor chip increases significantly as the scale of the system increases.

Conventionally, in the test of the ASIC microcomputer described above, each input terminal and output terminal of all circuit blocks other than an arbitrary one of a plurality of circuit blocks are set to a high impedance state, and one circuit block is set. Is separated from other circuit blocks, so that the function of each circuit block is individually tested.

FIG. 4 is a block diagram showing a schematic configuration of an example of such a conventional ASIC microcomputer.

A central processing unit (Central Processing Unit; hereinafter, also abbreviated as CPU) outside the semiconductor chip 1 during actual operation.
2 and input terminals 4 and 5 for supplying data and control signals to the individual circuit blocks of the peripheral circuits 3a and 3b, and output terminals 6 and 7 for extracting the output from each circuit block to the outside of the semiconductor chip 1. I have.

Apart from these terminals, a test is provided outside the semiconductor chip 1 for selectively setting any one of the circuit blocks to be electrically isolated from other circuit blocks so that a single test can be performed. A plurality of test input terminals 8a to 8n for inputting a mode setting signal are provided. The group of test input terminals 8a to 8n are connected to each circuit block,
The configuration is such that one circuit block is selected by a combination of signals input to these test input terminals.

The circuit block selected by the test mode setting signal is electrically separated from other circuit blocks, and a function test of the selected circuit block is performed under the separated state.

Problems to be Solved by the Invention However, apart from the input terminals used during actual operation as in the above-described conventional example, providing a plurality of dedicated test input terminals for inputting a test mode setting signal requires a large scale. As the number of circuit blocks constituting the ASIC microcomputer increases with the expansion, the number of test input terminals must be increased accordingly, which causes a problem that the cost is increased.

Therefore, an object of the present invention is to provide a semiconductor integrated circuit that can perform a function test for each circuit block without providing a dedicated test input terminal, and can reduce the cost.

Means for Solving the Problems According to the present invention, a plurality of circuit blocks each having an independent function are formed on one semiconductor chip, and one of the circuit blocks is used in a semiconductor integrated circuit which is a central processing unit. A reset terminal connected to the central processing unit, to which a reset signal is supplied; a plurality of input terminals shared between the actual operation and the test, connected to the circuit block; and a test state setting signal. A storage circuit for selectively separating one of the circuit blocks corresponding to the set test state setting signal from the other circuit blocks so as to enable a single test, and a predetermined one of the input terminals. In response to the output of the input terminal of the unit, a reset signal is supplied to the reset terminal, and at the same time, the actual operation of some of the input terminals is simultaneously performed with the reset signal. When a signal for a test that is not given is given, a test state setting signal given to a predetermined remaining input terminal among the input terminals is given to a memory circuit, and a reset signal is given at the same time as the reset signal. A semiconductor integrated circuit comprising: gate means for shutting off a connection between the remaining input terminal and the storage circuit when no signal is given.

According to the present invention, the reset terminal is connected to the central processing unit, the plurality of input terminals are connected to a plurality of circuit blocks including the central processing unit, and a reset signal is supplied to the reset terminal during actual operation, In a state where the signal for the test is not supplied to some of the input terminals, the gate means cuts off the connection between the remaining input terminals and the storage circuit. As a result, an actual operation without performing a function test for each circuit block can be performed.

At the time of a test, a reset signal is supplied to a reset terminal, and at the same time, a signal for the test is supplied to the some of the input terminals, whereby a test state setting signal from the predetermined remaining input terminals is passed through the gate means. To the storage circuit for storage. According to the test state setting signal stored in the storage circuit, one of the circuit blocks corresponding to the test state setting signal is selectively electrically separated from the other circuit blocks, and set to a state in which a single test can be performed. Thus, a functional test of the circuit block alone can be performed.

Moreover, according to the present invention, there is no need to provide a dedicated test input terminal.

Embodiment FIG. 1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

That is, in this semiconductor integrated circuit, the CPU 12 and the plurality of peripheral circuits 13a and 13b were formed on one semiconductor chip 11.
An ASIC microcomputer having input terminals 14, 15, 1 for supplying input signals to the CPU 12 and individual circuit blocks of the peripheral circuits 13a, 13b during actual operation outside the semiconductor chip 11.
6, 17 and the output of each circuit block
Output terminals 18 and 19 to be taken out are provided. The input terminal 16 among the input terminals 14 to 17 is a terminal for inputting a reset signal RESET for resetting the CPU 12,
The input terminal 17 is a predetermined input terminal of the CPU1.
2 is a terminal for inputting a wait signal WAIT that sets 2 to the operation wait state.

Of the input terminals other than the reset input terminal 16 and the wait input terminal 17, a predetermined remaining input terminal, for example, the input terminal 14 has a gate formed of a tristate buffer.
An n-bit (n is an integer) analog-to-digital converter (hereinafter abbreviated as A / D converter) 21 is connected via 20
Further, an n-bit test mode setting register 23 is connected to the next stage via a D flip-flop 22. The output terminal of the register 23 as this storage circuit is connected to the CPU1.
2. It is connected to each circuit block such as the peripheral circuits 13a and 13b.

The reset input terminal 16 and the wait input terminal 17 are separately connected to respective input terminals of a two-input NAND gate 24. The output terminal of the NAND gate 24 is connected to the connection terminal of the gate 20 and the D flip-flop 22. Connected to the clock input terminal CK. These gate 20, A / D converter 21, D flip-flop 22, and NAND gate 24 are
The gate means is constituted.

FIG. 2 shows an optional one of the above ASIC microcomputers.
9 is a timing chart showing a test mode setting operation when one circuit block is separated from another circuit block to perform a single function test. FIG. 3 is a flowchart showing the procedure of the function test. The procedure of the function test of the ASIC microcomputer will be described below with reference to FIGS.

In step n2 following the start of step n1, a low-level reset signal RESET is input to the input terminal 16 as shown in FIG. 2 (1), and in parallel with this, the input is made as shown in FIG. 2 (2). Low level wait signal on pin 17
Enter WAIT.

When the reset signal RESET is input to the CPU 12, the input terminal and the output terminal thereof become high impedance and become in an inactive state in which the input signal in the actual operation is not received. From the viewpoint of the operation of the entire microcomputer, it is a state that may be set even during actual operation, and does not necessarily mean a state during non-actual operation. On the other hand, as in this case, the reset signal RESET and the wait signal WAIT
Are input at the same time as during the actual operation, and this gives the test operation state, that is, the condition for setting the test mode.

While the reset signal RESET and the wait signal WAIT signal are being input in step n2, that is, during the mode setting period T shown in FIG. 2, the output of the NAND gate 24 is at a low level, and the gate 20 is turned on. That is, during this mode setting period T, one input terminal 14 used in the actual operation is connected to the A / D converter 21 via the gate 20. At this time, the D flip-flop 22 is also A /
It is set to take in the signal output from D converter 21.

In the next step n3, a test mode setting signal is input from the input terminal 14 during the mode setting period T. The test mode setting signal in this case is an analog signal for selectively setting one of the circuit blocks of the ASIC microcomputer that is electrically separated from other circuit blocks, and is associated with each circuit block. A plurality of types having different voltage levels are prepared.

An arbitrary test mode setting signal input to the input terminal 14 is input to the A / D converter 21 through the gate 20, where it is subjected to A / D conversion processing in step n4 to become an n-bit digital signal. The signal is sent to the register 23 via the D flip-flop 22. The transmission of this signal is stopped in response to the rise of the output signal of the NAND gate 24, that is, the gate 20 is turned off at the timing of the rise of the reset signal RESET and the wait signal WAIT, and the D flip-flop 22 is in the holding state. The test mode setting signal is stored in the register 23 as shown in FIG.

In the next step n6, in response to the test mode setting signal stored in the register 23, one circuit block designated by the signal makes itself electrically separated from other circuit blocks.

Thus, the separation of one circuit block is completed, and a function test is performed on the separated circuit block in the next step n7.

When the function test of one circuit block is completed, it is checked in step n8 whether or not the test of another circuit block remains. If the test of another circuit block remains, steps n2 to n9 are repeated to repeat each circuit. Perform functional tests sequentially for each block. When the function tests of all the circuit blocks are completed, the process proceeds to step n9, where all the processes are completed.

In the above-described embodiment, the logical product of the reset signal RESET and the wait signal WAIT is obtained to obtain the mode setting period T for capturing the test mode setting signal from the input terminal 14. Other signals that cannot be input simultaneously with the reset signal RESET signal may be combined with the reset signal RESET signal.

According to the present invention, according to the present invention, a reset terminal and a plurality of input terminals used in an actual operation in which an independent test of a circuit block is not performed are used as they are. A signal for the test is supplied to an input terminal of the unit, whereby a test state setting signal from the predetermined remaining input terminal is supplied to a storage circuit via a gate means and stored, and the test state thus stored is stored. One of the circuit blocks corresponding to the setting signal is selectively electrically separated from the other circuit blocks, so that a single test can be performed. In this way, the reset terminal and the plurality of input terminals used during the actual operation can be shared during the test, so that the number of terminals can be reduced, and the cost can be reduced accordingly.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 performs a functional test of each circuit block in the semiconductor integrated circuit. Timing chart showing the operation of the test mode setting in the case,
FIG. 3 is a flowchart showing a procedure of a function test of the semiconductor integrated circuit, and FIG. 4 is a block diagram showing a schematic configuration of a conventional semiconductor integrated circuit. 11: Semiconductor chip, 12: CPU, 13a, 13b: Peripheral circuit, 14, 15: Input terminal, 16: Reset input terminal, 1
7… Weight input terminal, 20… Gate, 21… A / D converter, 23… Register, 24… NAND gate

Claims (1)

(57) [Claims] A plurality of circuit blocks each having an independent function are formed on one semiconductor chip, and one of the circuit blocks is connected to the central processing unit in a semiconductor integrated circuit that is a central processing unit. A reset terminal to which a reset signal is supplied, a plurality of input terminals which are shared between the actual operation and the test and are connected to the circuit block, and a test state setting signal which is stored. A memory circuit for selectively separating one of the circuit blocks corresponding to the above from the other circuit blocks so as to enable a single test, and an output of a predetermined part of the input terminals among the input terminals In response to the reset signal, the reset signal is supplied to the reset terminal, and at the same time, in the actual operation, the reset signal is not supplied to some of the input terminals. When a signal for a test is given, a test state setting signal given to a predetermined remaining input terminal among the input terminals is given to a memory circuit, and a signal for the test is not given at the same time as a reset signal. A gate circuit for shutting off the connection between the remaining input terminal and the storage circuit.