JPH0424833A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To carry out the function tests for each circuit block without using any test-only input terminal by connecting the prescribed one of those input terminals that are used for real operations to a storage circuit via a gate while a reset signal is inputted to a reset terminal. CONSTITUTION:When a reset signal is inputted to a reset input terminal 16 to reset a CPU, the prescribed terminal 16 is connected to a storage circuit 12 among those input terminals which are used during an actual operation of a gate 20. Under such conditions, the test state setting signal inputted to an input terminal 14 is stored in a storage circuit 23 via the gate 20. Then a circuit block selected by the stored test state setting signal is separated from other circuit blocks. Thus a function test can be applied to a single circuit block. Then the number of terminals is decreased and the reduction of cost is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit in which a plurality of circuit blocks each having independent functions, such as a microprocessor and peripheral circuits, are formed on one semiconductor chip.

Conventional technology In recent years, with the improvement of semiconductor integrated circuit manufacturing technology, semiconductors (hereinafter referred to as ASICs) have been developed for specific applications in which multiple circuit blocks each having independent logic functions, such as a microprocessor and peripheral circuits, are formed on a single semiconductor chip. Complex integrated circuits such as microcomputers (called microcomputers) have begun to be developed.

In the case of a complex integrated circuit such as the above-mentioned ASIC microcomputer, all the circuits constituting one system are formed on one semiconductor chip, which is a so-called system-on-chip configuration.As the scale of the system increases, the number of semiconductor chips increases. The number of circuit blocks for each function described above will also increase significantly.

Conventionally, in testing the above-mentioned ASIC microcomputer, one circuit block is tested by setting each input terminal and output terminal of all the circuit blocks except one of the plurality of circuit blocks to a high impedance state. By separating the circuit blocks from other circuit blocks, the functionality of each circuit block was tested individually.

FIG. 4 is a block diagram showing a schematic configuration of an example of such a conventional ASIC microcomputer.

External to the semiconductor chip 1 is a central processing unit (
An input terminal 4.5 that supplies data and control signals to the individual circuit blocks of the Central Processing Unit (hereinafter also abbreviated as CPU) 2 and each peripheral circuit 3a, 3b, and outputs from each circuit block to the outside of the semiconductor chip 1. Output terminals 6 and 7 are respectively provided.

Apart from these terminals, there is a test external to the semiconductor chip 1 for selectively electrically isolating any one of the circuit blocks from other circuit blocks to enable independent testing. A plurality of test input terminals 8a to 8n are provided to input mode setting signals. The - group of test input terminals 8a to 8n is connected to each circuit block, and is configured to select one circuit block based on a combination of signals input to these test input terminals.

The circuit block selected by the test mode setting signal is electrically isolated from other circuit blocks, and the function test of the selected circuit block is performed under the isolated state.

Problems to be Solved by the Invention However, it is difficult to provide a plurality of dedicated test input terminals for inputting test mode setting signals in addition to the input terminals used during actual operation as in the conventional example described above.
When the number of circuit blocks constituting an ASIC microcomputer increases as the scale of the ASIC microcomputer increases, the number of test input terminals must increase accordingly, resulting in an increase in cost.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor integrated circuit that can perform a functional test for each circuit block without providing a dedicated test input terminal, and can reduce costs.

Means for Solving the Problems The present invention provides a semiconductor integrated circuit in which a plurality of circuit blocks including a central processing unit each having independent functions are formed on one semiconductor chip. a memory circuit that holds a test state setting signal for selectively electrically isolating one of the blocks from other circuit blocks and setting it in a state where it can be tested independently, and supplies it to each circuit block; and a central processing unit. A gate that connects a predetermined input terminal among input terminals used during actual operation to the memory circuit when a reset signal is input to a reset input terminal that inputs a reset signal for resetting the semiconductor integrated circuit from outside the semiconductor integrated circuit. A semiconductor integrated circuit characterized by comprising:

According to the present invention, when a reset signal for resetting the central processing unit is input to the reset input terminal, the gate connects a predetermined input terminal among the input terminals used during actual operation to the memory circuit. Under this state, when a test state setting signal is input to the input terminal, the signal is stored in the memory circuit through the gate, and one circuit block selected by the stored test state setting signal is connected to the other circuit block. It is separated from the circuit block, making it possible to test the functionality of the circuit block alone.

Embodiment FIG. 1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit which is an embodiment of the present invention.

That is, this semiconductor integrated circuit includes a CPU 12 and a plurality of peripheral circuits 13a and 13b on one semiconductor chip 11.
An ASIC microcomputer formed with
Outside the semiconductor chip 11, there are input terminals 14, 15, 16, 17 that provide input signals to the CPU 2 and the individual circuit blocks of the peripheral circuits 13a and 13b during actual operation, and output terminals of each circuit block to the outside of the semiconductor chip 11. Output terminals 18, 19 for taking out are provided. Its input terminals 14-1
7, the input terminal 16 is a terminal for inputting a reset signal RESET for resetting the CPU 12, and the input terminal 17 is a terminal for inputting a wait signal WAIT for setting the CPU 12 to a standby state.

One of the input terminals excluding the reset input terminal 16 and the wait input terminal 17, for example, the input terminal 14
is connected to an n-bit (n is an integer) analog-to-digital converter (hereinafter referred to as an A/D converter) 21 via a gate 20 consisting of a tri-state buffer, and the next stage is a D An n-bit test mode setting register 23 is connected via a flip-flop 22 . The output terminal of this register 23 is connected to each circuit block such as the CPU 12 and peripheral circuits 13a and 13b.

Further, the reset input terminal 16 and the wait input terminal 17 are respectively connected to respective input terminals of a two-man power NAND gate 24, and the output terminal of this NAND gate 24 is connected to the control terminal of the gate 20 and the D flip-flop 20. is connected to the clock input terminal CK of.

FIG. 2 is a timing chart showing the operation of setting a test mode when an arbitrary one circuit block of the ASIC microcomputer is separated from other circuit blocks and an independent functional test is performed. Further, FIG. 3 is a flowchart showing the procedure of the functional test. Referring to FIGS. 2 and 3, the procedure for testing the functionality of the ASIC microcomputer will be described below.

In step n2 following the start of step n1, the second
As shown in Figure (1), a low level reset signal RESET is input to the input terminal 16, and in parallel with this, as shown in Figure 2 (
As shown in 2), the wait signal WAIT, which is also at a low level, is input to the input terminal 17.

When the reset signal RESET is input to the CPU 12,
Its input and output terminals become high impedance and are in an inactive state in which they do not receive input signals during actual operation, but the input of such a reset signal RESET is important from the perspective of the overall operation of the ASIC microcomputer. In this case, it is a state that may be set during actual operation, and it cannot necessarily be said that it refers to the state during non-actual operation.

On the other hand, as in this case, the reset signal RESE
The input condition that T and the wait signal WAIT are input simultaneously is a condition that does not exist during actual operation, and this provides a condition for setting the test mode in the test operation state.

While the reset signal RESET and wait signal WAIT signal are being input in step n2, that is, during the mode setting period T shown in FIG. 2, the output of the NAND gate 24 is at a low level, and the gate 20 is turned on. That is, during this mode setting period T, one input terminal 14 used during actual operation is connected to the A/
When the baby is 0 years old and connected to the D converter 21, the D flip-flop 22 is also set to take in the signal output from the A/D converter 21.

In the next step n3, a test mode setting signal is input from the input terminal 14 during the mode setting period T. The test mode setting signal in this case is an analog signal for selecting and setting one circuit block that is electrically isolated from other circuit blocks among the circuit blocks of the ASIC microcomputer, and is associated with each circuit block. Multiple types with different voltage levels are available.

Any test mote setting signal input to the input terminal 14 is input to the A/D converter 21 via the gate 20, where it undergoes A/D conversion processing in step n4 to become an n-bit digital signal. The signal is D flip-flop 2
2 and is sent to the register 23. The transmission of this signal is N
The gate 20 is turned off at the timing of the rise of the output signal of the AND gate 24, that is, the rise of the reset signal RESET and the wait signal WAIT, and the D flip-flop 22 is stopped in response to the holding state, as shown in step n5. The test mode setting signal is stored in the register 23.

In the next step n6, in accordance with the test mode setting signal stored in the register 23, one circuit block specified by the signal electrically isolates itself from other circuit blocks.

With the above steps, separation of one circuit block is completed, and in the next step n7, a functional test is performed on the separated circuit block.

When the functional test of one circuit block is completed, it is checked in step n8 whether there are any tests remaining for other circuit blocks. If tests for other circuit blocks remain, steps n2 to n9 are repeated to test each circuit. Perform functional tests sequentially for each block. When the functional test of all circuit blocks is completed, the process moves to step n9, and all processing is completed here.

In the above embodiment, the mode setting period T during which the test mode setting signal is taken in from the input terminal 14 is obtained by taking the logical product of the reset signal RESET and the wait signal WAIT. The reset signal RESET signal may be combined with other signals that cannot be input simultaneously with the reset signal RESET signal.

Effects of the Invention As described above, according to the semiconductor integrated circuit of the present invention, while a reset signal is input to the reset terminal, a predetermined input terminal among the input terminals used during actual operation via the gate is connected to the memory circuit. Since the test state setting signal is connected to the memory circuit during this period, the test state setting signal can be stored in the memory circuit using the input terminal. That is, since the input terminals used during actual operation can also be used as input terminals for testing, the number of terminals can be reduced, and costs can be reduced accordingly.

[Brief explanation of the drawing]

・Figure 1 is a block diagram showing the schematic configuration of a semiconductor integrated circuit that is an embodiment of the present invention, and Figure 2 is a diagram showing test mode settings when performing a functional test of each circuit block alone in the semiconductor integrated circuit. FIG. 3 is a flowchart showing the procedure of a functional test of the semiconductor integrated circuit, and FIG. 4 is a block diagram showing the schematic configuration of the conventional semiconductor integrated circuit. 11. Semiconductor chip, 12. CPU, 13a13
b... Peripheral circuit, 14.15... Input terminal, 16 Reset input terminal, 17... Wait input terminal, 2
0...-gate, 21... A/D converter, 23...
Register, 24...NAND Gate Agent Patent Attorney Stroke Number Keiichi Diagram Diagram

Claims (1)

[Claims] In a semiconductor integrated circuit in which a plurality of circuit blocks including a central processing unit each having an independent function are formed on a single semiconductor chip, an input signal from outside the semiconductor integrated circuit that controls one of the circuit blocks. A memory circuit that holds and supplies a test state setting signal to each circuit block for selectively electrically separating it from other circuit blocks to enable independent testing; and a memory circuit for resetting the central processing unit. and a gate that connects a predetermined input terminal among the input terminals used during actual operation to the memory circuit when the reset signal is input to the reset input terminal that inputs the reset signal from outside the semiconductor integrated circuit. A semiconductor integrated circuit characterized by: