JPH11142476A - Semiconductor integrated circuit and its inspection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time required for setting a logic signal for inspection which is given to a circuit block while suppressing an increase in the number of external input terminals in an inspection method of a semiconductor integrated circuit including the circuit block having a plurality of input terminals. SOLUTION: The output terminals of toggle type flip-flops 101 to 104 are connected to a plurality of input terminals 401 to 404 of a circuit block 301, respectively, and the toggle operation control terminals of the toggle type flip- flops 101 to 104 are connected to the output terminals of a decoder 1101 incorporated in a semiconductor integrated circuit. Also the input terminals of the decoder 1101 are connected to the external input terminals 1301 and 1302 of the semiconductor integrated circuit, respectively. Then the toggle operation of the toggle type flip-flops 101 to 104 is controlled for each flip-flop by a signal given from an outside to the semiconductor integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit including one or a plurality of circuit blocks having a plurality of input terminals, and a method for testing the same.

[0002]

2. Description of the Related Art In such an inspection of a semiconductor integrated circuit, an inspection is generally performed for each circuit block (also referred to as a functional block) in order to suppress an increase in an inspection time due to recent large-scale integration. It is. For example, for each functional block, a test signal of a predetermined logic pattern is input from a plurality of input terminals to check whether a normal signal is output or not. An example of a conventional method for providing such a plurality of logic signals to a plurality of input terminals of a circuit block will be described with reference to FIG.

In FIG. 5, reference numeral 301 denotes a circuit block included in a semiconductor integrated circuit to be inspected.
2, 403 are input terminals of this circuit block. 11
1, 112 and 113 are flip-flops, and their outputs are input terminals 401 and 40 of the circuit block 301.
2 and 203 respectively. Although FIG. 5 shows only three input terminals of the integrated circuit 301,
Actual integrated circuits have more input terminals,
The same number of flip-flops are provided.

Further, the output of the first flip-flop 111 becomes the input 212 of the second flip-flop 112, and the output of the second flip-flop 112 becomes the input of the third flip-flop. Are connected to form a shift register. Of the signals input to each flip-flop, reference numeral 801 denotes a test signal which becomes active when a test is performed. 501, 502, and 503 are clock signals. Reference numerals 601, 602, and 603 are input signals for performing a normal operation, and are connected to internal signal lines of the semiconductor integrated circuit.

In the above-described circuit configuration, when performing a normal operation, the inspection signal 801 is set to an inactive level. As a result, the flip-flops 111, 112, 11
The three valid input signals are 601, 602, and 603.
These signals are supplied to the flip-flops 111, 112, 1
13, the input 40 of the circuit block 301 is latched.
1, 402, 403.

On the other hand, when performing a test, a test signal 801 is set to an active level. Then, the flip-flop 11
The valid input signals of 1, 112, 113 are 211, 21
2, 213. Therefore, the clock signal 501,
When a serial signal input 211 is provided to the first flip-flop 111 from outside the integrated circuit in synchronization with the flip-flops 502 and 503, the serial signal
1, 112, and 113 are shifted and latched one bit at a time, and output as parallel outputs to input terminals 401, 402, and 403 of the circuit block 301.

[0007]

As described above, in the inspection of a circuit block of a semiconductor integrated circuit, a method of converting a serial signal input into a parallel signal by using a shift register circuit and then applying the converted signal to an input terminal of the circuit block is as follows. This has the advantage that only one test input terminal is required, but has the disadvantage that the time required for inputting the test signal is long. Especially,
When the number of input terminals of a circuit block to be inspected increases, the time required to apply a signal of a predetermined inspection pattern to all input terminals becomes a major obstacle to a demand for shortening the inspection time.

On the other hand, if an attempt is made to directly apply the test pattern to the input terminals of the circuit block as parallel data, it is necessary to provide the same number of external connection terminals as the number of input terminals, so this method is not practical.

In view of the above, the present invention has improved an input method of an inspection pattern signal in the conventional inspection method as described above,
It is an object of the present invention to provide an inspection method capable of reducing the time required for input. It is another object of the present invention to realize a configuration of a semiconductor integrated circuit that can perform the inspection method while suppressing an increase in external connection terminals.

[0010]

A semiconductor integrated circuit according to the present invention includes one or a plurality of circuit blocks having a plurality of input terminals, and each of the plurality of input terminals of the circuit block has a toggle flip-flop. Are connected, and the toggle operation of the toggle flip-flop is controlled for each flip-flop by a signal externally applied to the semiconductor integrated circuit.

Preferably, the toggle operation control terminals of the plurality of toggle flip-flops connected to the plurality of input terminals of the circuit block are connected to the output terminal of a decoder built in the semiconductor integrated circuit, and the input terminal of the decoder is connected to the semiconductor terminal. It is connected to the external input terminal of the integrated circuit.

According to the inspection method of the present invention for a semiconductor integrated circuit having the above configuration, when predetermined logic data is supplied to a plurality of input terminals of a circuit block, the logic data to be held among a plurality of toggle flip-flops is provided. Only for flip-flops whose logic data differs from the logic data to be given to the input terminal,
It is characterized in that predetermined logic data is given to a plurality of input terminals.

According to the above-described semiconductor integrated circuit and the test method thereof, the time required for providing predetermined logic data to a plurality of input terminals of a circuit block can be shortened as compared with the related art. In testing a circuit block, it will usually not be necessary to invert all logic data at the input terminals. Rather, the number of flip-flops that need to be toggled can be reduced by devising the inspection procedure to minimize the number of bits of the inspection pattern to be applied to the circuit block that should be inverted in successive inspection steps.

Further, by interposing a decoder between the external input terminal and the input terminal of the circuit block, the required number n of external input terminals is significantly smaller than the number m of input terminals of the circuit block (for example, m is equal to 2 to the power of n). In this case, the number of flip-flops that can be toggled by one external input at one time is limited to one. However, as described above, the number of flip-flops to be toggled is reduced. The input of a predetermined test pattern can be completed in a short time.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit block included in a semiconductor integrated circuit according to an embodiment of the present invention and a signal input circuit thereof. In FIG. 1, reference numeral 301 denotes a circuit block to be inspected, and reference numerals 401, 402, and 403 denote input terminals of the circuit block. Reference numerals 101, 102, and 103 denote toggle flip-flops.
01, 702, and 703 are connected to input terminals 401, 402, and 203 of the circuit block 301, respectively. Although FIG. 1 shows only three input terminals of the integrated circuit 301, an actual integrated circuit has more input terminals and the same number of toggle flip-flops.

Each toggle flip-flop 10
1, 102 and 103 have clock signals 501 and 50, respectively.
2, 503 and input signals 601, 602, 6 during normal operation
03 is connected. Input signals 601, 602, 60
3 is connected to the internal signal line of the semiconductor integrated circuit. In addition, an inspection signal 801 which becomes an active level when an inspection is performed and toggle operation control signals 210, 202, and 203 for activating a toggle operation are connected to the respective toggle flip-flops 101, 102, and 103.

FIG. 2 shows a toggle flip-flop 10.
A truth table of 1, 102 and 103 is shown. In FIG.
Reference numeral 1001 denotes a clock signal input, which corresponds to the clock signals 501, 502, and 503 in FIG. An inspection signal input 1002 corresponds to the clock signal 801 in FIG.
A toggle operation control signal input 1003 corresponds to the toggle operation control signals 201, 202, and 203 in FIG. 1
004 is a data input, and the input signals 601 and 6 in FIG.
02, 603. Reference numeral 1005 denotes a data output, which corresponds to the output signals 701, 702, and 703 in FIG.

In the inspection of the semiconductor integrated circuit including the circuit block and its input circuit shown in FIG. 1, for example, among the data held in the toggle flip-flops 101, 102 and 103, the input terminal 4 of the circuit block 301
It is assumed that only the input terminal 403 has a bit different from the test data to be given to 01, 402, and 403. In this case, if the toggle control signal 203 is set to the active level (H level) while the check signal 801 is at the active level (H level), the data held in the toggle flip-flop 103 is inverted at the rising edge of the clock signal 503. , Desired test data are input to the input terminals 401 and 4 of the circuit block 301.
02,403.

Next, FIG. 3 shows an example of a circuit including the above-described circuit block and input circuit, and further connecting an external input terminal to a toggle control signal terminal of each toggle flip-flop via a decoder. In FIG. 3, reference numeral 301 denotes a circuit block to be inspected, and 401, 402, 403,
404 is an input terminal of this circuit block. 101,
Reference numerals 102, 103, and 104 denote toggle flip-flops having the function of the truth table shown in FIG. 2, and output signals thereof are input terminals 401, 402 of the circuit block 301 via wirings 701, 702, 703, and 704, respectively. , 40
3 and 404, respectively.

Each toggle flip-flop 101, 10
The clock signal input terminals 2, 103 and 104 are connected to the wiring 52.
1 through an external clock input terminal 12 of the semiconductor integrated circuit
04. Each toggle flip-flop 1
The test signal input terminals 01, 102, 103 and 104 are connected to the external input terminal 120 of the semiconductor integrated circuit through the wiring 811.
3 is connected. Input signals 601, 6 during normal operation
02, 603 and 604 are connected to internal signal lines of the semiconductor integrated circuit.

The input terminals 401, 4 of the circuit block 301
02, 403, and 404 to provide test data.
4 are the input signal terminals 201, 202, 203, and 2
04 are connected to four output terminals of the decoder 1101. Two input terminals of the decoder 1101 are connected to external input terminals 1201 and 1202 of the semiconductor integrated circuit through wirings 1301 and 1302, respectively.
The decoder circuit 1101 performs the operation shown in the truth table of FIG. 4, 1401 and 1402 correspond to two input signals (external input terminals 1201 and 1202 in FIG. 3), and 1403, 1404, 1405, and 1406 correspond to four output signals (wirings 201, 202, 203, and 203 in FIG. 3). 20
This corresponds to 4). According to the 2-bit input signal, only one bit of the 4-bit output goes high.

In the circuit shown in FIG. 3, for example, it is assumed that all flip-flops 101, 102, 103 and 104 hold L level. The input terminals 401, 402, 403, and 404 of the circuit block are L, H,
It is assumed that an inspection is performed by inputting L and H level logic signals, respectively. In this case, the number of toggle flip-flops that need to be inverted by a toggle operation is 10
2 and 104. From the truth table of FIG. 4, when the input 1401 (external input terminal 1301) is set to H level and the input 1402 (external input terminal 1302) is set to L level, only the output 1404 (wiring 202) becomes H level.
It can be seen that the toggle flip-flop 102 performs an inversion operation. Similarly, when the inputs 1401 and 1402 (external input terminals 1301 and 1302) are both at H level, only the output 1406 (wiring 204) is at H level, and the toggle flip-flop 104 inverts.

Therefore, with the external input terminal 1203 connected to the test signal input terminal of each toggle flip-flop via the wiring 811 at the active level (H level), the external input terminal 1201 is first set to the H level. , 12
02 is set to the L level, the toggle flip-flop 10 is set at the timing of the rising edge of the clock signal input from the external clock input terminal 1204.
2 (input 402 of the circuit block 301) changes from H level to L level. Next, the external input terminal 12
By setting both 01 and 1202 to H level,
The output of the toggle flip-flop 104 at the timing of the rising edge of the clock signal (the circuit block 301)
Input 404) changes from H level to L level.

In the input of inspection data in the conventional inspection method using a shift register, it is necessary to input data in four steps in order to set logical data of four input terminals. Then, data input with a smaller number of steps (two steps in the above example) is sufficient. One of the four input terminals to be logically inverted is 1
If the number is only one, one-step data input is sufficient.

In the above example, the test data is supplied to the four input terminals of the circuit block by the data input from the two external input terminals using the 2-4 decoder. By inputting data from n external input terminals, test data can be supplied to 2 n input terminals. For example, in order to provide test data to 1000 input terminals, it is sufficient if there are 10 external input terminals.

[0026]

As described above, according to the semiconductor integrated circuit and the test method of the present invention, the external connection of the semiconductor integrated circuit can be shortened while reducing the time required for inputting the test pattern signal to the circuit block. An increase in the number of terminals can be suppressed.

[Brief description of the drawings]

FIG. 1 is a circuit block included in a semiconductor integrated circuit according to an embodiment of the present invention and its signal input circuit;

FIG. 2 is a diagram showing a truth table of a toggle flip-flop used in the signal input circuit of FIG. 1;

FIG. 3 is a circuit diagram showing a test signal input circuit of a circuit block of a semiconductor integrated circuit in the test method of the present invention.

FIG. 4 is a diagram showing a truth table of a decoder used in the test signal input circuit of FIG. 4;

FIG. 5 is a circuit diagram showing a test signal input circuit of a circuit block of a semiconductor integrated circuit in a conventional test method.

[Explanation of symbols]

101-103, 111-114 Toggle flip-flops 201-204 Toggle operation control signals of toggle flip-flops (or their wiring) 301 Circuit blocks to be inspected 401-404 Input terminals 501-503, 521 of circuit blocks to be inspected Clock signal input and wiring 601 to 604 Internal data input signal of toggle flip-flop 701 to 704 Output signal of toggle flip-flop 801, 811 Test signal input of toggle flip-flop 1001 Clock input terminal of toggle flip-flop 1002 toggle Inspection control terminal of flip-flop 1003 Toggle operation control terminal of toggle flip-flop 1004 Data input terminal of toggle flip-flop 1005 Data output terminal of toggle flip-flop Child 1101 Decoder circuit 1201, 1202 External input terminal connected to input terminal of decoder circuit 1203 External input terminal connected to test control terminal of toggle flip-flop 1204 External input connected to clock input terminal of toggle flip-flop Terminals 1301 and 1302 Wiring from external input terminals to input terminals of decoder circuit 1401 and 1402 Input terminals of decoder circuit 1403, 1404, 1405 and 1406 Output terminals of decoder circuit

Claims (3)

[Claims] 1. A semiconductor integrated circuit including one or a plurality of circuit blocks having a plurality of input terminals, wherein an output terminal of a toggle flip-flop is connected to each of a plurality of input terminals of the circuit block. A semiconductor integrated circuit, wherein a toggle operation of the toggle flip-flop is controlled for each flip-flop by a signal externally applied to the circuit. 2. A toggle operation control terminal of a plurality of toggle flip-flops connected to a plurality of input terminals of the circuit block is connected to an output terminal of a decoder built in a semiconductor integrated circuit, and an input terminal of the decoder is connected to an output terminal of the decoder. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is connected to an external input terminal of the semiconductor integrated circuit. 3. The method for testing a semiconductor integrated circuit according to claim 1, wherein predetermined logic data is supplied to a plurality of input terminals of said circuit block, and said plurality of toggle flip-flops are retained. Inspecting a semiconductor integrated circuit, wherein predetermined logic data is applied to the plurality of input terminals by performing a toggle operation only on flip-flops whose logic data to be applied is different from the logic data to be applied to the input terminal. Method.