JPH10125085A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain reduction of cost, low power consumption and shortening of testing time due to reduction in size of circuit by arranging an FF circuit for scanning cell in the first and final stages of the shift register for scanning. SOLUTION: In a semiconductor integrated circuit having a shift register circuit for scanning, a shift register circuit 10 for n-bit scanning inputs an output data of a combining circuit 11 in the input side and serially fetches this input in synchronization of a clock pulse signal for the purpose of shifting. A combining circuit 12 in the output side inputs a serial output data of the shift register circuit 10 for scanning. The shift register circuit 10 for scanning replaces the D-type FF circuit in the first stage and the D-type FF circuit in the final stage among the D-type FF circuits of the n-bit shift register circuit with the FF circuit 90 for scan cell and uses an ordinary D-type FF circuit 20 as it is for the intermediate stage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a design technology for facilitating test for efficiently performing self-diagnosis of an internal logic circuit of a semiconductor integrated circuit, and more particularly to a digital LSI such as a standard cell used in a specific application field. And is used, for example, in an LSI incorporating a video signal processing circuit.

[0002]

2. Description of the Related Art In recent years, with the progress of LSI technology, high integration of logic circuits has been remarkable. The large-scale and high-integration of the logic circuit has brought advantages such as functional improvement and weight reduction of various devices using the logic circuit.However, on the other hand, the test of the logic circuit itself and the creation of test data for it have been very difficult. Making it difficult. Therefore, in the design stage of a logic circuit, a so-called test facilitating design, which employs a design in consideration of a test, has been gradually used.

In the conventional design for testability, a technique called a scan design system and a technique of adding a self-test circuit called a compact test system are becoming common.

[0004] The scan design system directly sets the state of a flip-flop (FF) circuit of the logic circuit inside the integrated circuit by scan-in from outside the integrated circuit, and inputs the setting data to a combinational circuit to operate. Output the state of the combinational circuit after the operation to the FF circuit and scan it out so that the state can be observed.
This is to improve the testability of the LSI (improve the failure detection rate). In other words, the input / output of the scan cell FF circuit is regarded as an external terminal of the integrated circuit, thereby replacing the test of the sequential circuit with the test of the combinational circuit.

FIG. 8 shows an example of a conventional n-bit shift register circuit used in a video signal processing circuit. The n-bit shift register circuit shown in FIG. 8 includes an n-stage D-type FF circuit 20, and the combination circuit 1 on the input side.
One output data DO is input, serially fetched and shifted in synchronization with the clock pulse signal CP, and the serial output data is output as input data DN and DNN of the combination circuit 12 on the output side.

FIG. 9 shows an n-bit scan shift register circuit in which each D-type FF circuit 20 in FIG. 8 is replaced with a scan cell FF circuit 90. In this case, a plurality of scan cell FF circuits 90 are cascaded and connected in series in the direction from the scan-in terminal SI to the scan-out terminal SO.

As is well known, a D-type FF circuit 20 shown in FIG. 8 receives a master-slave type D-type FF circuit 30 controlled by a complementary clock signal and a system clock signal. A clock driver for generating the complementary clock signal.

The scan cell FF circuit 9 shown in FIG.
0 is a master-slave type D-type FF circuit 30 controlled by a complementary clock signal, the scan-in terminal SI and the D-type FF circuit 3
A scan-in circuit 31 that is connected between the data hold circuit on the master side and the scan-in control signal A and is controlled to be in an off state in the normal mode / on for a certain time in the scan mode by the scan-in control signal A; A scan-out circuit connected between the data holding circuit on the slave side of the circuit 30 and the scan-out terminal, controlled by a scan-out control signal B, and controlled to be in an off state in a normal mode / an on state for a predetermined time in a scan mode. 3
2 and a clock driver that receives the system clock signal, generates the complementary clock signal, and supplies the clock signal to a required circuit.

The operation of the scan FF circuit 90 in the normal mode is the same as that of the conventional D-type FF circuit 20 in a state where the scan-in circuit 31 and the scan-out circuit 32 are controlled to be off. .

That is, the output data DO of the combination circuit 11 on the input side is input, the data is serially captured and shifted in synchronization with the clock pulse signal CP, and the serial output data is input to the input circuit of the combination circuit 12 on the output side. Output as DN, DNN.

On the other hand, the operation of the scan cell FF circuit 90 in the scan mode is performed when the scan-in control signal A is in the active state and the clock signal CP is at the "H" level. Scan-in data is imported from Then, when the scan-in control signal A becomes inactive, the D-type FF circuit 3
Data is held on the master side of 0.

Next, when the scan-out control signal B is activated, scan-out data is output from the scan-out terminal SO. Then, when the scan-out control signal B is activated, the scan-out terminal SO is brought into a floating state.

That is, in the scan shift register circuit of FIG. 9, each scan cell FF circuit 90 is controlled to a different operation state according to the normal mode / scan mode as described above, and is synchronized with the clock signal CP. Perform a shift operation.

In this case, during normal operation, each scan cell FF circuit 90 operates in the same manner as the conventional D-type FF circuit 20, and operates in the same manner as the shift register circuit in FIG. On the other hand, in the scan mode, each scan cell FF circuit is controlled to perform a scan operation,
The test input data SI from the outside is applied to the first stage FF circuit 90.
Scan-in, and the test output data SO is scanned out from the final FF circuit 90 to the outside.

However, the scan shift register circuit shown in FIG. 9 uses a scan cell FF circuit for all of the FF circuits at each stage of the n-bit shift register circuit. As compared with the type FF circuit, the number of circuits used is larger by the scan-in circuit and the scan-out circuit, and the pattern size is large. The chip size becomes large, resulting in a significant cost increase.

In other words, the conventional scan shift register circuit has an excessively large overhead on the chip area, and thus requires low cost LS for consumer TV and VTR.
In the case of I, there was a problem that it was difficult to adopt it from the viewpoint of cost.

The scan shift register circuit shown in FIG. 9 consumes a large amount of power because of the large number of circuits used.
Since control signals A and B and scan data pass through all stages of the n-bit shift register circuit, there is also a problem in terms of test time.

The scan cell FF circuit is not limited to the above-described specific example, and may be used in various configurations having the same basic functions and improved various characteristics. As long as the number of elements is large, there is the same problem as described above.

[0019]

As described above, the conventional scan shift register circuit has an excessively large overhead in terms of chip area, so that cost reduction is required for consumer TV and VTR LSIs that require low cost. From the viewpoint of power consumption and test time.

The present invention has been made to solve the above-mentioned problems, and is suitable for use in fields such as consumer TVs and VTRs which require a reduced circuit size and low cost. It is an object of the present invention to provide a semiconductor integrated circuit having a scan shift register circuit capable of reducing power and reducing test time.

[0021]

According to a semiconductor integrated circuit of the present invention, a combinational circuit on the input side and output data of the combinational circuit on the input side are input, and the data is serially captured in synchronization with a clock pulse signal. A scan shift register circuit of n bits to be shifted, and a combination circuit on an output side to which serial output data of the scan shift register circuit is input, wherein the scan shift register circuit is a first stage scan cell FF circuit The intermediate D-type FF circuit and the final stage scan cell FF circuit are cascaded, and the signal of the scan-out terminal of the first stage scan cell FF circuit is input to the scan-in terminal of the final stage scan cell FF circuit. FF circuits of each stage are connected so that a clock signal is supplied to each stage. Characterized by comprising a Torejisuta circuit.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a part of a semiconductor integrated circuit according to a first embodiment of the present invention.

In FIG. 1, reference numeral 11 denotes an input-side combinational circuit, and 10 denotes an n-bit scanning circuit which receives the output data of the input-side combinational circuit, serially captures and shifts the data in synchronization with a clock pulse signal. The shift register circuit 12 is a combination circuit on the output side to which serial output data of the scan shift register circuit is input.

The scan shift register circuit 10
Represents each D of the n-bit shift register circuit shown in FIG.
The first stage D-type FF circuit and the last stage D-type FF circuit of the type FF circuits are replaced with a scan cell FF circuit 90,
The intermediate stage uses the ordinary D-type FF circuit 20 as it is.

That is, in the scan shift register circuit 10, the first stage scan cell FF circuit 90, the intermediate stage D-type FF circuit 20, and the last stage scan cell FF circuit 90 are cascaded, and the first stage scan cell circuit is connected. For F
The signal of the scan-out terminal SO of the F circuit 90 is connected so as to be input to the scan-in terminal SI of the scan FF circuit 90 of the last stage, and the clock signal CP is supplied to the FF circuit of each stage.

The ordinary D-type FF circuit 20 and the scan cell FF circuit 90 are the same as those in the conventional example, respectively. In a cell-based LSI, for example, they are configured as shown in FIGS. 2 and 3, respectively. I have.

The D-type FF circuit 20 shown in FIG. 2 has a master circuit controlled by complementary clock signals (φ, / φ).
The slave type D-type FF circuit 60 and the system clock signal CP are input, and the complementary clock signals (φ, /
φ) is generated.

The master-slave type D-type FF circuit 60 includes a data input terminal D, a pair of complementary output terminals Q and / Q, a transmission gate 61 controlled by an inverted clock signal / φ, and a clock. , A transmission gate 63 and a clocked inverter 64 controlled by a clock signal φ, and inverters 65 to 67.

The clock driver 21 comprises two-stage inverter circuits 22 and 23 to which a system clock signal CP is inputted, and generates a clock signal φ and an inverted clock signal / φ.

The scan cell FF circuit 90 shown in FIG.
Is between the master-slave type D-type FF circuit 30 controlled by complementary clock signals (φ, / φ) and the scan-in terminal SI and the data holding circuit on the master side of the D-type FF circuit 30 And a scan-out circuit 42 connected between the data holding circuit on the slave side of the D-type FF circuit 30 and the scan-out terminal SO.

The master-slave type D-type FF circuit 30 has a data input terminal D, a pair of complementary output terminals Q and QN (/ Q), and a clocked signal controlled by an inverted clock signal / φ. Inverters 31 and 32
A clocked inverter 33 controlled by a clock signal φ, a clocked inverter 34 controlled by a scan-in control signal A, a transmission gate 35 controlled by a clock signal φ, and inverters 36 to 39 Consists of

The scan-in circuit 41 is controlled by a scan-in control signal A so as to be in an off state in the normal mode and to be in an on state for a certain time in the scan mode. For example, the scan-in circuit 41 is controlled by a scan-in inversion control signal / A. Clocked inverter.

The scan-out circuit 42 is controlled by a scan-out control signal B. The scan-out circuit 42 is controlled to be in an off state in a normal mode / an on state for a predetermined time in a scan mode. The transmission gate 44 and the inverter 45 controlled by B are cascaded in this order.

The scan-in inversion control signal /
A is generated by the inverter circuit 46 to which the scan-in control signal A is input, and the scan-out inversion control signal / B is generated by the inverter circuit 47 to which the scan-out control signal B is input.

The clock driver 21 includes two-stage inverter circuits 22 and 23 to which a system clock signal CP is input, generates a clock signal φ and an inverted clock signal / φ, and supplies the clock signal to a required circuit. .

The scan cell FF circuit 90 shown in FIG.
The operation in the normal mode is similar to the operation of the conventional D-type FF circuit 20 in a state where the scan-in circuit 41 and the scan-out circuit 42 are each controlled to the off state.

That is, the output data DO of the combinational circuit 11 on the input side is input, serially fetched and shifted in synchronization with the clock pulse signal CP, and the serial output data is converted to the input data of the combinational circuit 12 on the output side. Output as DN, DNN (/ DN).

On the other hand, the operation of the scan cell FF circuit 90 in the scan mode is performed when the scan-in control signal A is in the active state and the clock signal CP is at the "H" level. Scan-in data is imported from Then, when the scan-in control signal A becomes inactive, the D-type FF circuit 3
Data is held on the master side of 0. Next, when the scan-out control signal B is activated, scan-out data is output from the scan-out terminal SO. Then, when the scan-out control signal B becomes inactive, the scan-out terminal SO becomes floating.

As described above, according to the scan shift register circuit of FIG. 1, the scan FF circuit 9 in the first stage and the last stage according to the normal mode / scan mode.
0 is controlled to a different operation state as described above, and performs a shift operation in synchronization with the clock signal CP.

In this case, during normal operation, the scan cell FF circuit 90 operates similarly to the conventional D-type FF circuit 20, and operates similarly to the operation of the conventional n-bit shift register circuit shown in FIG. I do.

On the other hand, in the scan mode, the scan cell FF circuit 90 is controlled so as to perform a scan operation, the test input data SI from the outside is scanned into the first stage FF circuit 90, and the final stage FF circuit 90 is scanned. The test output data SO from the circuit 90 is scanned out.

The above-described scan shift register circuit is composed of the first stage D-type FF circuit 20 and the last stage D-type F-type circuit among the stage circuits of the conventional n-bit shift register circuit.
Each of the F circuits 20 is replaced with a scan cell FF circuit 90, and the intermediate stage uses the ordinary D-type FF circuit 20 as it is.

Thus, all stages of F as shown in FIG.
As compared with the conventional scan shift register circuit using the scan FF circuit 90 as the F circuit, the number of circuits used in the intermediate D-type FF circuit 20 is smaller, the pattern size is smaller, and power consumption is reduced. It becomes possible to reduce.

Accordingly, the register size is reduced as a whole, the chip size is reduced, the cost can be reduced, and it is suitable for use in fields such as consumer TVs and VTRs where low cost is required. .

Further, since the control signals A and B for scanning and the scan data do not pass through all stages of the n-bit shift register circuit, they pass only through the first stage FF circuit 90 and the last stage FF circuit 90. In addition, the test time can be reduced. This can greatly reduce the test cost, which is an important factor in determining the price of the LSI.

The pattern of the scan shift register circuit in FIG. 1 may be laid out by automatic placement and routing using a layout CAD (computer-aided design) system, but is surrounded by a dotted line in FIG. By arranging the scan shift register circuit portion as a macro block and forcibly or closely arranging it on the layout, it is possible to simplify the routing of the system clock CP line, the scan control signals A and B lines, and the shift data line. And the layout size can be reduced.

Further, the simplification of the clock line can reduce the wiring load, reduce the pattern size of the clock buffer in the scan cell FF circuit, and consequently reduce the power consumption of the clock system. Further, the simplification of the clock line makes it possible to easily distribute the clock while improving the skew problem (reducing the skew).

FIG. 4 shows a scan shift register circuit which is divided into macro blocks according to a second embodiment of the present invention. The scan shift register circuit 10a shown in FIG. 4 is different from the scan shift register circuit 10 shown in FIG. 1 in that a system clock input is input to a system clock driver 51 composed of a group of inverter circuits 48 to 50 when forming a macroblock. Then, complementary system clocks CP and CPN (/ CP) are generated, and these are fed to the first stage scan cell F / F circuit 90a, the middle stage D-type F / F circuit 20a, and the last stage scan cell F / F circuit 20a. The difference is that the supply is supplied to the F circuit 90a.

In this case, the intermediate D-type F / F circuit 20a
5, that is, the complementary clock signal (φ, //) in the D-type F / F circuit 20 shown in FIG.
The clock driver 21 for φ) can be omitted, and a modified one can be used in which complementary system clocks CP and CPN are used as complementary clock signals (φ, / φ).

The first and last stage scan cell F / F circuits 90a are configured as shown in FIG.
The clock driver 21 for the complementary clock signal (φ, / φ) in the scan cell F / F circuit 90 shown in FIG. 3 is omitted, and the complementary system clocks CP, CP are omitted.
A configuration in which the N inputs are changed so as to be used as complementary clock signals (φ, / φ) can be adopted.

Thus, the circuit configuration can be further simplified,
Clock skew can be easily managed, the pattern size can be further reduced, and the power consumption of the clock system can be further reduced.

Although each stage of the scan shift register circuit in FIGS. 1 and 4 uses an example using a static register, the invention is not limited to this, and a dynamic register may be used.

FIG. 7 shows a scan shift register circuit which is divided into macro blocks according to the third embodiment of the present invention. The n-bit scan shift register circuit 10b shown in FIG. 7 is different from the n-bit scan shift register circuit 10 shown in FIG. The D-type FF circuit in the intermediate stage is replaced with a dynamic D-type FF circuit 20b, and the output terminal Q of each circuit is connected to the data input terminal D of the next stage.

Then, instead of the clock pulse signal CP, two-phase clock pulse signals CP1 and CP2 are supplied to clock terminals CP1 and CP2 of each stage circuit via buffer circuits 71 and 72, respectively, and control signals A and B are supplied. Instead, the clock pulse signal CP3 is supplied to the control input terminal CP3 of each circuit via the buffer circuit 73, and the output terminal Q of the first stage scan cell FF circuit 90b is connected to the last stage scan cell FF circuit. 90b to the scan-in input terminal SI. The scan shift register circuit of FIG. 7 having the above configuration operates substantially in the same manner as the scan shift register circuit shown in FIG. 1, and achieves the same effects.

[0055]

As described above, according to the present invention, consumer TVs and VTs requiring a reduced circuit size and low cost are required.
It is suitable for use in fields such as R, and can realize a semiconductor integrated circuit having a scan shift register circuit capable of reducing power consumption and reducing test time.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a scan shift register circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a D-type F / F circuit in the scan shift register circuit of FIG. 1;

FIG. 3 is a circuit diagram showing an example of a scan cancel F / F circuit in the scan shift register circuit of FIG. 1;

FIG. 4 is a circuit diagram showing a scan shift register circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing an example of a D-type F / F circuit in the scan shift register circuit of FIG. 4;

6 is a circuit diagram showing an example of a scan cell F / F circuit in the scan shift register circuit of FIG. 4;

FIG. 7 is a circuit diagram showing a scan shift register circuit according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram showing a conventional shift register circuit.

FIG. 9 is a circuit diagram showing a conventional scan shift register circuit.

[Explanation of symbols]

10, 10a, 10b: scan shift register circuit, 11: combination circuit on input side, 12: combination circuit on output side, 20, 20a, 20b: D-type FF circuit, 21: clock driver, 30: master / slave method 41, a scan-in circuit, 42, a scan-out circuit, 90, 90a, 90b, a scan cell FF circuit, SI, a scan-in terminal, and SO, a scan-out terminal.

Claims (9)

[Claims] An input-side combinational circuit; an n-bit scan shift register circuit that receives output data of the input-side combinational circuit, serially captures and shifts the data in synchronization with a clock pulse signal, A combination circuit on the output side to which serial output data of the scan shift register circuit is input, wherein the scan shift register circuit includes a first stage scan cell FF circuit, an intermediate stage D-type FF circuit, and a final stage The scan cell FF circuits are cascaded and connected so that the signal of the scan-out terminal of the first-stage scan cell FF circuit is input to the scan-in terminal of the final-stage scan cell FF circuit. A semiconductor integrated circuit to which a system clock signal is supplied. 2. The semiconductor integrated circuit according to claim 1, wherein the D-type FF circuit receives a master-slave type D-type FF circuit controlled by a complementary clock signal, and receives a system clock signal. A clock driver for generating a complementary clock signal. 3. The semiconductor integrated circuit according to claim 1, wherein the scan cell FF circuit includes a master-slave D-type FF circuit controlled by a complementary clock signal, a scan-in terminal, and the scan-in terminal. A scan-in circuit connected between the D-type FF circuit and a data holding circuit on the master side, the scan-in circuit being controlled in an off state in a normal mode / an on state for a fixed time in a scan mode by a scan-in control signal; A scan-out circuit connected between the data holding circuit on the slave side of the FF circuit and the scan-out terminal, controlled by a scan-out control signal, and controlled in an off state in a normal mode / an on state for a fixed time in a scan mode; , A system clock signal is input, the complementary clock signal is generated, and the clock is supplied to a required circuit. The semiconductor integrated circuit characterized by comprising a clock driver for supplying a click signal. 4. The semiconductor integrated circuit according to claim 1, wherein said scan shift register circuit is formed as a macro block. 5. An n-bit scanning shift circuit for receiving input data from an input-side combinational circuit and inputting the output data from the input-side combinational circuit and serially capturing and shifting the data in synchronization with a complementary system clock pulse signal. A register circuit; a combination circuit on an output side to which serial output data of the scan shift register circuit is inputted; and a clock driver to which a system clock signal is inputted and which generates the complementary system clock signal. The shift register circuit includes a cascade connection of a first stage scan cell FF circuit, an intermediate stage D-type FF circuit and a last stage scan cell FF circuit. Input to the scan-in terminal of the stage scan cell FF circuit It is continued, a semiconductor integrated circuit, characterized in that the complementary system clock signal to the FF circuit of each stage is supplied. 6. The semiconductor integrated circuit according to claim 5, wherein said D-type FF circuit is a master-slave type D-type FF controlled by said complementary system clock signal.
A semiconductor integrated circuit, which is a circuit. 7. The semiconductor integrated circuit according to claim 5, wherein said scan cell FF circuit is a master-slave D-type FF circuit controlled by said complementary system clock signal, and a scan-in terminal. A scan-in circuit that is connected between the data-hold circuit on the master side of the D-type FF circuit and is controlled to be in an off state in a normal mode / an on state for a fixed time in a scan mode by a scan-in control signal; Scan-out connected between the data holding circuit on the slave side of the D-type FF circuit and the scan-out terminal, controlled by a scan-out control signal, and controlled to be in an off state in a normal mode / an on state for a certain time in a scan mode A semiconductor integrated circuit, comprising: a circuit; 8. The semiconductor integrated circuit according to claim 5, wherein said scan shift register circuit is formed as a macro block. 9. An n-bit scan shift register for receiving an input combinational circuit and output data of the input-side combinational circuit, serially acquiring and shifting the output data in synchronization with a two-phase clock pulse signal. And a combination circuit on the output side to which serial output data of the scan shift register circuit is input, wherein the scan shift register circuit is a first stage dynamic type scan cell FF circuit and an intermediate stage dynamic type. D-type FF circuit and the final stage dynamic scan cell FF circuit are cascaded, and the signal of the data output terminal of the first stage scan cell FF circuit is input to the scan-in terminal of the final stage scan cell FF circuit And scans the scan FF circuits of the first and last stages. A semiconductor integrated circuit, wherein the two-phase clock pulse signal is supplied to the FF circuit of each stage.