JPH0677050B2 - Electronic circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an electronic circuit having an inspection function.

2. Description of the Related Art Conventionally, in a monolithic semiconductor integrated circuit, a test circuit used only at the time of inspection is added when the circuit scale integrated on one chip is large or the circuit is complicated. In this case, the semiconductor integrated circuit is divided into a plurality of functional blocks, and the optimum signal for inspecting each functional block is
The function test of the electronic circuit device is performed by using a test terminal indicating a test state and a test mode input terminal indicating which functional block is inspected so as to be able to directly input or output.

FIG. 3A shows a conventional circuit example. IN1 to 4 are input terminals, OUT1 and OUT2 are output terminals, TEST is a test signal input terminal for inputting a signal indicating a test state, and TMODE is a test mode input for determining which functional block is to be inspected. Terminals A, B and C are functional blocks, D is a test circuit control block, SW1 to 4 are switches, and the signals necessary for inspecting the functional blocks A, B and C are directly input terminals IN1 to IN4. , SW1 to SW4 are connected to the output terminals OUT1 and OUT2, and the switching of the signals of SW1 to SW4 is controlled by the signal from the test circuit control block.

FIG. 3B shows the switching directions of the switches SW1 to SW4 in the input state of the test signal input terminal TEST and the test mode input terminal TMODE. As shown in FIG. 3 (b), when the test signal input terminal TEST is at "L" level, it is in a normal operation state, and the switches SW1 to SW4 are all connected to the side a.
However, if the test signal input terminal TEST is at the "H" level, the test state is entered, and the switches SW1 to SW4 are connected to the a side or the b side by the "H" and "L" of the test mode switching terminal TMODE. It

When the semiconductor integrated circuit device is in a test state, that is, when the test input terminal TEST is at “H” level, it is divided into two modes by the test mode input terminal TMODE,
When the test mode input terminal TMODE is "L", the functional block A can directly input the signal input to the functional block A from the input terminals IN1 and IN2, and the output of the functional block A is directly output from the output terminal OUT1. You can see it. The functional block C can directly input the signal input to the functional block C using the input terminals IN3 and IN4.
The output of can be inspected from output terminal OUT2.

Next, when the test mode input terminal TMODE is set to “H” level, all input signals to the functional block B are
Input can be made from IN1, IN2, IN3, and the output of the functional block B can be directly inspected through the output terminal OUT1.

Problems to be Solved by the Invention However, the above test circuit has the following problems. In other words, as the circuit scale increases and becomes more complex, it becomes necessary to divide it into many functional blocks for inspection, and along with this, the number of input terminals for creating the test mode increases, and it is used by the user. There is a problem that the number of impossible terminals increases.

The present invention solves such a problem. In order to eliminate a test mode input terminal dedicated for a test, the function is given to a terminal used in a normal state, and the test mode input function is provided even during a test. It is an object of the present invention to enable many test modes to be created with the minimum number of terminals by making it possible to inspect a given terminal without losing the original meaning of the terminal.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention is connected to an input terminal used in a normal state, and when the test state is entered, “H” and “L” of the input terminal are connected. A latch circuit for storing "is provided, and the output of the latch circuit is used as a test mode setting signal.

Operation With this configuration, many test modes can be created without having a test mode input terminal, and a terminal provided with a test mode input function can be inspected without losing the original meaning of the terminal.

Embodiment FIG. 1 is a test mode setting circuit diagram according to an embodiment of the present invention. TEST is a test input terminal, IN1 and IN2 are input terminals, 1 and 2 are latches, 3 is a test control block, and latches 1 and 2 take in data at the rising edge of the clock input. Further, TA and TB are test mode signals, S1 is an input signal from the input terminal IN1, S2 is an input signal from the input terminal IN2, and S3 is a test signal from the input terminal TEST. The test signal S3 is at "H" level in the test state, and is at "L" level in the normal operation state.

The data inputs of latches 1 and 2 are the input signal S1 respectively.
And S2, the clock input is the test signal S3,
When the clock input rises, that is, enters the test state, the level of the data input is latched and output to Q to generate the test mode signals TA and TB. The test control block 3 receives the input signal S3, the test mode TA and the test mode TB, and can create up to four test modes. A signal from the test mode control block 3 controls changeover switches between many functional blocks.

FIG. 2 is a test mode setting circuit diagram according to another embodiment of the present invention. TEST is the test input terminal, S13 is the input terminal T
Test signal from EST, 10 is a test clock generation circuit for generating a pulse signal S14 at the rise of the test signal, 11 and 12 are input signals S11, S12 from input terminals IN1, 2 with the pulse signal S14 as a clock input. Is a data input, and its output is connected to the test control block 13 as test mode signals TSA and TSB. That is, the test mode signals TSA and TSB are created by latching the input signals S11 and S12 at the rising edge of the test signal S13. In the embodiment shown in FIG. 2 as well, like the embodiment shown in FIG. 1, a maximum of four test modes can be created.

EFFECTS OF THE INVENTION As described above, according to the present invention, a test input terminal only for creating a test mode is not required, and it also serves as a normal input terminal, but the function of the normal input terminal is lost. It is possible to create a large number of test modes without any trouble, and detailed inspection can be performed for inspection of a large-scale circuit or a complicated electronic circuit device, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a test mode generating circuit according to an embodiment of the present invention, FIG. 2 is a circuit block diagram showing a test mode generating circuit according to another embodiment of the present invention, and FIG. ) Is a conventional test circuit, and FIG. 3 (b) is a diagram showing a combination of switch switching in each test mode. TEST …… Test input terminals, IN1, IN2 …… Input terminals, 3,13
...... Test control block, 1,2,11,12 …… Latch, 10 …… Inspection clock generation circuit.

Claims (1)

[Claims] 1. A latch circuit for inputting a signal at a rising edge of a clock input is connected to each of a plurality of inputs, and the output of the latch circuit and one test signal are input to a test control block, An electronic circuit that creates multiple test modes.