JP2557703B2 - Mode setting circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to an integrated circuit in which various functions are mixed,
The present invention relates to a mode setting circuit that sets an operation mode of the circuit.

(B) Conventional technology In a highly integrated integrated circuit device (hereinafter referred to as an IC), various functions are mounted together to expand the range of use. Such a multi-function IC is usually constructed so that it can operate in a large number of modes, and the setting of its operation mode poses a problem.

FIG. 4 is a block diagram of a mode setting circuit for setting the operation mode of the IC as described above. The main circuit (1) is, for example, a timing signal generation circuit having a gate array configuration and is configured to generate various timing clocks based on a basic clock CK supplied from the outside, and operates according to a mode setting signal. The mode is set. This operation mode can be set in a number equal to the number of bits of the mode setting signal. For example, 4-bit mode setting signals M _{1 to} M ₄ can be set.
According to the above, four kinds of modes can be set, that is, one of the mode setting signals M _{1 to} M ₄ is set to “1”,
Since "0" is set in the other bits, the main circuit (1) operates in the mode corresponding to the bit in which "1" is set. Decoder (2), which operates in accordance with a selection signal S _1, S ₂ for selecting the operation mode, selection signals S _1,
Outputs a mode setting signal M ₁ ~M ₄ of "1" is set only for the bits indicated by S _2. The selection signal requires a bit number corresponding to the type of mode to be set (bit number of the mode setting signal), and requires 2 bits when there are four types of operation modes.

(C) Problem to be Solved by the Invention Generally, the decoder (2) and the main circuit (1) are provided on the same substrate (3), and a selection signal is input to the substrate (3) from the outside. It will be. Therefore, if the number of operation modes of the main circuit (1) is large, the number of bits of the selection signal is large, so that the number of bits of the signal input to the substrate (3) is large. Therefore, when integrated into an IC, the number of terminals is increased.

If it is desired to reduce the size and weight of the device by high-density mounting, the number of terminals in the IC mounted on the device will increase and the wiring inside the device will increase. Become.

In addition, since the number of IC terminals is limited to some extent, if the number of input terminals for mode setting increases, the number of output terminals will not be sufficient and it will be difficult to operate the IC functionally. .

(D) Means for Solving the Problems The present invention has been made to solve the above problems, and has n bits (n bits) in a main circuit unit capable of operating in a plurality of modes.
In the mode setting circuit for selectively setting the operation mode of the main circuit section by giving a mode setting signal of 2 or more), the first feature is that a plurality of main circuits are provided. Of n outputs are connected to one of the inputs of the n logic gates, and one output selected from the n outputs is connected to the other of the inputs of the logic gate. The purpose is to obtain an n-bit mode setting signal based on the output of the logic gate.

The second characteristic is that the first of n bits is
Each bit of the output of the counter is connected to one of the inputs of the n logic gates, and is output from the output of the n-bit second counter which is counted by the clock common to the first counter and reset at the same timing. The selected 1 bit is connected to the other of the inputs of the logic gate,
The purpose is to obtain an n-bit mode setting signal based on the outputs of the n logic gates.

(E) Operation According to the present invention, by selecting one of the output of the main circuit or the output of the second counter and supplying it to each input of the n logic gates, A specific output is obtained from one of the logic gates, and the mode setting signal in which only the bit corresponding to the logic gate from which the specific output is obtained is set to a value different from other bits can be obtained.

Therefore, when n logic gates are provided on the same substrate as the main circuit, the operation mode of the main circuit is set by inputting one signal selected from the output of the main circuit or the output of the second counter. .

(F) Embodiments Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a mode setting circuit of the present invention, showing a 4-bit configuration, that is, a case where there are four kinds of operation modes. The main circuit (1) outputs various timing clocks CK based on the basic clock CK as in FIG. 4, of which four types of timing clocks T _{1 to} T ₄ are used for mode setting. The timing clocks T _{1 to} T ₄ are the first to fourth EXs, respectively.
One of the timing clocks T _{1 to} T ₄ is selected by the switching circuit (5) while being connected to one input of the OR (exclusive OR) gates (4a) to (4d). The timing clock selected by the switching circuit (5) is connected to the other of the inputs of the EXOR gates (4a) to (4d). Each EXOR
The gates (4a) to (4d) output the determination signals m _{1 to} m ₄ , respectively, and output “0” when both inputs match,
In other cases, "1" is output. Therefore, the output of EXOR gates to which the same timing pulse is input to both inputs is always "0", and the output of other EXOR gates is
"0" and "1" are repeated. This repeating pattern follows the timing pulse and differs depending on each timing pulse.

Then, the setting signal generating circuit (6) determines the judgment signals m _{1 to} m ₄
Among them, the mode setting signals M _{1 to} M _{4 in} which only the bit corresponding to the signal which is always “0” is “1” are output. Therefore, for example, when the switching circuit (5) selects the timing pulse T ₃ , both inputs of the EXOR gate (4c) always match, the determination signal m ₃ is always “0”, and the mode setting signal M ₃ is “1”. It will be. At this time, the determination signals m ₁ , m ₂ and m ₄ repeat “1” and “0” in accordance with the timing pulses T ₁ , T ₂ and T ₄ , and the mode setting signals M ₁ , M ₂ and M ₄ are It becomes "0". Therefore, the main circuit (1) is
The operation mode corresponding to M ₃ is set.

Such a mode setting circuit has EXOR gates (4a) ~
(4b) and the setting signal generating circuit (6) are provided on the same substrate (3 ') as the main circuit (1), and the switching circuit (5) is externally provided. That is, the changeover switch is externally attached to the one-chip IC on the board (3 '), and the signals from the IC output terminals (7a) to (7d) are selectively applied to the mode setting terminal (8). Configured to give. According to the above configuration, since the mode setting can be performed using the output terminals (7a) to (7d) originally provided in the IC, only one mode setting terminal is required. Therefore, even if the number of operation modes increases, it is not necessary to increase the number of terminals within the range of the number of output terminals.

FIG. 2 is a block diagram showing another embodiment of the present invention.
In this figure, the EXOR gates (4a) to (4d), the setting signal generating circuit (6) and the main circuit (1) are the same as those in FIG. 1 and are designated by the same reference numerals.

The first step counter (11) is counted by the basic clock CK and reset by the reset pulse RS, and the outputs Q _{11 to} Q ₁₄ are connected to one inputs of the EXOR gates (4a) to (4d), respectively. It On the other hand, the second step counter (12) is the same as the first step counter (11) and is counted by the basic clock CK, and the reset pulse RS
The first step counter by being reset by (11)
Is synchronized with. The outputs Q _{21 to} Q ₂₄ of the second step counter (12) match the outputs Q _{11 to} Q _{14 of} the first step counter (11), respectively, and the switching circuit (13)
, One of the outputs Q _{21 to} Q ₂₄ is selected and connected to the other input of each EXOR gate (4a) to (4d). Therefore, as in the case of FIG. 1, the decision signals m _{1 to} m ₄ obtained from the EXOR gates (4a) to (4d) are either ones depending on the outputs Q _{21 to} Q ₂₄ selected by the switching circuit (13). one Although would be fixed at "0", only either one bit in accordance with the determination signal is "1" and becomes mode setting signal M ₁ ~M ₄ is obtained from a setting signal generator circuit (6).

In this mode setting circuit, the first step counter (11) is the same as the main circuit (1) in addition to the EXOR gates (4a) to (4d) and the setting signal generating circuit (6) as in FIG. Is provided on the substrate (3 ″) of the above, and the second step counter (12) and the switching circuit (13) are externally provided. That is, for an IC integrated into one chip on the substrate (3 ″). The step counter and the changeover switch which are the same as the built-in first step counter (11) are externally attached to the IC, and the output of the step counter is selectively applied to the mode setting terminal (8). According to the above configuration, in addition to the mode setting terminal (8), the input terminal (9) of the basic clock CK for synchronizing the first and second step counters (11) (12) and the reset pulse SR 3 with output terminal (10)
The operation mode can be set with the terminal. Further, the basic clock CK can be shared with that input to the main circuit (1). Therefore, by increasing the number of bits of both step counters (11) and (12), many operation modes can be taken without increasing the number of input terminals for mode setting.

FIG. 3 is a circuit diagram showing an example of the setting signal generating circuit (6) described above.

R (reset) of flip-flops (61a) to (61d)
The determination signals m _{1 to} m ₄ are input to the terminals, respectively, and the output of the OR circuit (62) is input to the S (set) terminal. The Q outputs of the flip-flops (61a) to (61d) are input to one of the inputs of the AND gates (63a) to (36d), respectively, and also to the determination circuit (64). The judgment circuit (64)
"1" is output when the input 4-bit signal becomes "1" by 1 bit, and "0" is output when "1" is 2 bits or more. The output of the decision circuit (64) is input to the other of the inputs of the AND gates (63a) to (63d), and the outputs of the AND gates (63a) to (36d) are 4-bit mode setting signals M _{1 to} M. It is output as ₄ .

On the other hand, the outputs of the flip-flops (61a) to (61d) are input to the NOR gate (65), the operation mode is changed, and all the outputs of the flip-flops (61a) to (61d) become "0". When this happens, "1" is given to the input of the OR gate (62). The power-on reset signal PR is input to the OR gate (62) and
The logical sum of the output from the NOR gate (65) is input to the S terminals of the flip-flops (61a) to (61d). Therefore, each of the flip-flops (61a) to (61d) is initialized by the output of the OR gate (62), and each Q output becomes "1". Therefore, when the determination signals m _{1 to} m ₄ become “1”, the Q outputs of the corresponding flip-flops become “0”, and the three Q outputs of the flip-flops (61a) to (61d) become “0”. The output of the judgment circuit (64) becomes "1" when it becomes
Mode setting signals M _{1 to} M ₄ are output from the D gates (63a) to (63d). That is, among the determination signals m _{1 to} m ₄ , the signal corresponding to the operation mode to be set is fixed to “0”, while the other signals can be “1” at a certain timing, so “0” is set. The mode setting signals M _{1 to} M _{4 in} which the bit for the determination signal fixed to “1” is “1” are obtained.

In order to prevent malfunction due to noise, the reliability of the flip-flops (61a) to (61d) can be improved by synchronizing the reading of signals into the S and R terminals of the flip-flops (61a) to (61d) with the basic clock CK. Can be achieved.

In the above embodiments, the mode setting circuit having a 4-bit structure capable of setting four kinds of operation modes has been exemplified.
It is easily obtained that five or more kinds of operation modes can be set as a configuration of more than one bit.

(G) Effect of the Invention According to the present invention, it is possible to increase the number of operation mode settings without increasing the number of input terminals. Therefore, it is possible to reduce the number of terminals of a multifunction IC having many operation modes. , It is effective in reducing the size and weight of the device equipped with this IC.

In addition, in an IC with a limited number of terminals, the reduced number of input terminals can also be used as an output terminal, so that the IC can be functionally operated, and effective use of functions can be expected.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the mode setting circuit of the present invention, FIG. 2 is a block diagram showing another embodiment, and FIG. 3 is an example of the setting signal generating circuit of FIGS. 1 and 2. FIG. 4 is a circuit diagram showing a conventional mode setting circuit. (1) …… Main circuit, (2) …… Decoder, (3)
(3 ') (3 ") ... substrate, (4a) to (4d) ... EXOR gate, (5) (13) ... switching circuit, (6) ... setting signal generating circuit, (7a) to ( 7d) …… Output terminal, (8) …… Mode setting terminal, (11) (12) …… Step counter.

Claims (2)

(57) [Claims] 1. A mode setting for selectively setting an operation mode of the main circuit section by applying an n-bit (n is an integer of 2 or more) mode setting signal to the main circuit section operable in a plurality of modes. In the circuit, n exclusive OR gates provided on the same substrate as the main circuit section and having n outputs of the main circuit section respectively connected to one of the inputs, and the main circuit section n output terminals connected to the n outputs respectively and taken out from the board, a mode setting terminal commonly connected to the other of the inputs of the n exclusive OR gates, and a mode setting terminal provided outside the board. Selecting means for selecting one of the n output terminals and connecting it to the mode setting terminal, and a specific one bit in response to the output of each of the n exclusive OR gates. N-bit mode setting signal that indicates a state different from And a setting signal generating unit that outputs the setting signal generating unit, and operates the selecting unit according to the selection of the operation mode of the main circuit unit. 2. A mode setting for selectively setting an operation mode of the main circuit section by giving an n-bit (n is an integer of 2 or more) mode setting signal to the main circuit section operable in a plurality of modes. In the circuit, an n-bit first counter that is provided on the same substrate as the main circuit unit and that counts in response to a clock, and an output of each bit of the first counter that is provided on the substrate N exclusive OR gates respectively connected to one of the inputs, a second counter provided outside the substrate and counting in response to a clock common to the first counter, and the n exclusive logics A mode setting terminal commonly connected to the other input of the sum gate, and provided outside the substrate,
Selection means for selecting one bit of the output of the second counter and connecting it to the mode setting terminal, and a specific one bit in response to each output of the n exclusive OR gates is replaced with another bit. A setting signal generating means for outputting an n-bit mode setting signal indicating a different state, and the selecting means is operated according to the selection of the operation mode of the main circuit section.