JP2924030B2 - Clock signal selection circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal selection circuit, and more particularly to a clock signal selection circuit that selects and outputs different clock signals to a plurality of functional blocks.

[Conventional technology]

Conventionally, this kind of clock signal selection circuit has a circuit configuration shown in FIG.

In FIG. 4, a clock signal CK input from the outside
Is input to the six-stage frequency dividing circuit 21. The six-stage frequency dividing circuit 21 divides the frequency of the clock signal CK and outputs a signal after each frequency division. When the frequency of the clock signal CK was f _x, divided output
a, b, c, d, e, f are f _x / 2, f _x / 4, f _x / 8, f _x / 16, f _x / 32,
A clock signal with a frequency of f _x / 64. The mode register H is a register for setting which of the divided outputs c, d, e, and f is to be output to the clock output CKOUT1, and in this case, in order to select four types of divided outputs, Requires a 2-bit register. The selector D: 22 selects one of the frequency-divided outputs c, d, e, and f according to the data set in the mode register H: 26, and outputs it as the clock output CKOUT1. Table 1 shows an example of the set value of the mode register H: 26 and the frequency-divided output output to the clock output CKOUT1.
In this example, when “01” is set in the mode register H: 26, the frequency output d is output to the clock output CKOUT1.

FIG. 5 is a circuit example of the selector D: 22 in FIG. In this case, since only one signal is selected and output from the four types of signals, four AND gates 30 to 33 and one OR gate 34 are provided. Thus, the selector circuit is a relatively large circuit.

Similarly, any one of the divided outputs c, d, e, and f is output to the clock outputs CKOUT2, CKOUT3, and CKOUT4 according to the values set in the respective mode registers I: 27, J: 28, and K: 29. Is.

FIG. 6 shows an example of an operation timing chart. This timing chart shows the clock outputs CKOUT1, CKOUT2, CKOU
This is an operation example in the case where frequency-divided outputs d, f, c, and d are selected and output as T3 and CKOUT4, respectively.

[Problems to be solved by the invention]

The above-described conventional clock signal selection circuit requires a selector circuit having a relatively large circuit scale for each clock output, and thus has the disadvantage that when it is implemented as an LSI, the circuit becomes complicated and the chip area increases.

[Means for solving the problem]

A clock signal selection circuit according to the present invention includes a timing circuit for generating first and second latch signals in response to a clock signal, an input terminal connected to the first node, and an output terminal connected to the first output terminal. A first latch circuit connected to the first latch signal for receiving the data of the input terminal in response to the first latch signal; and an input terminal connected to the first node and an output terminal connected to the second output terminal. A second latch circuit that captures data at the input end in response to the second latch signal; a first mode register; a second mode register; and a second mode register corresponding to the first latch signal. A first selector that outputs the value of the second mode register and outputs a value of the second mode register for a period corresponding to the second latch signal; and a first selector that is generated in response to the clock signal. Clock and the second The divided clock is input first
And a second selector that outputs the first or second frequency-divided clock selected at the first node in accordance with a value supplied from the selector.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of one embodiment of the present invention. The clock signal CK input from the outside is input to the six-stage frequency dividing circuit 1. Operation of a six-stage divider circuit 1 is the same as the conventional example described above, when the frequency of the clock signal CK and the f _x, the frequency of the divided output a, b, c, d, e, f , respectively , F _x / 2, f _x / 4, f
_{x / 8, f x / 18} , f x / 32, is f _x / 64.

The mode registers H: 14, I: 15, J: 16, and K: 17 are 2
Clock output CKOUT1, CKOUT2, CK
Which of the divided outputs c, d, e, and f is output is set to OUT3 and CKOUT4. The selector B: 3 and the selector C: 4 correspond to the upper and lower bits of the mode register, respectively. When the frequency-divided outputs a and b are both LOW level, the selector B: 3 selects and outputs the upper bit of the mode register H: 14, and the selector C: 4 selects and outputs the lower bit of the mode register H: 14. I do. Similarly, when the divided outputs a and b are at the high level and the low level, respectively, the mode register I: 1
5.When low level and high level, mode register J: 1
6. When the signal is at the high level, the setting value of the mode register K: 17 is selected and output.

The selector A determines the output value of the selectors B and C
One of the divided outputs c, d, e, and f is selected and output. The output of the selector A has four clock output latches 5, 6, 7, 8
Is input to The output of the clock output latch 5 is the clock output CKOUT1, and similarly, the clock output latches 6, 7, 8
Are clock outputs CKOUT2, CKOUT3, and CKOUT4.

The timing decoder 13 is a circuit that decodes the frequency-divided outputs a and b. The output of the timing decoder 13 and signals g, h, i, j obtained by ANDing the clock signal CK are provided in four clock output latches, respectively. 5, 6, 7 and 8 are latch signals.

FIG. 2 is an operation timing chart for explaining the operation of the example of the present invention. Divided outputs a and b of clock signal CK
However, when both are at the low level, the selectors B: 3 and C: 4
Select and output the mode register H. Therefore, at this time, the selector A: 2 in FIG. 1 outputs any one of the divided outputs c, d, e, and f according to the set value of the mode register H: 14. The clock signal CK is the output latch signal g of the clock output CKOUT1 when both the divided outputs a and b are at the low level. Similarly, when the divided outputs 9 and b are at the high level and the low level, respectively, one of the divided outputs c, d, e, and f is selected according to the set value of the mode register I: 15, and The output CKOUT2 is latched by the output latch 6.

FIG. 3 is an example of an operation timing chart of the example of the present invention. In this example, the clock outputs CKOUT1, CKOUT2, CKOUT3, C
This is the case where the divided outputs d, f, c, d are selected for KOUT4. In this embodiment, the clock output CKOU is
T1, CKOUT2, CKOUT3, and CKOUT4 are out of phase with each other, but have the same clock output as the frequency (cycle).

[Effects of the Invention] As described above, the present invention has a common selector for selecting and outputting a divided output in each clock output, and selecting and outputting each clock output in a time-sharing manner, thereby reducing the circuit scale. There is an effect that the chip area can be reduced when the LSI is made smaller. In the present embodiment, an example has been described in which four clock outputs are time-divided, but this effect is more remarkable as the number of clock outputs increases. The effect is also great when there are many clock types to be selected.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a clock signal selection circuit of the present invention,
2 is a timing chart for explaining the operation of FIG. 1, FIG. 3 is an example of an operation timing chart of FIG. 1, FIG. 4 is a circuit configuration diagram of a conventional clock signal selection circuit, and FIG. FIG. 6 is a circuit diagram of the selector of FIG. 4, and FIG.
It is an example of the operation timing chart of the figure. 1,21 ... 6-stage frequency divider, 2, 3, 4, 22, 23, 24, 25 ... selector circuit, 5, 6, 7, 8 ... latch, 9, 10, 11, 12, 30, 30, 31,32,33
…… AND gate, 13 …… Timing decoder, 14,15,16,
17, 26, 27, 28, 29, 37 ... mode register, 34 ... OR gate, 35, 36 ... inverter.

Claims (1)

(57) [Claims] A timing circuit for generating first and second latch signals in response to a clock signal;
A first latch circuit connected to the first node and having an output terminal connected to the first output terminal and receiving the data of the input terminal in response to the first latch signal; and an input terminal connected to the first node. A second latch circuit that is connected and has an output terminal connected to a second output terminal and takes in data of the input terminal in response to the second latch signal; a first mode register;
A second mode register for outputting a value of the first mode register for a period corresponding to the first latch signal and outputting a value of the second mode register for a period corresponding to the second latch signal; 1 selector, and a first divided clock and a second divided clock generated in response to the clock signal are input to the first node in accordance with a value supplied from the first selector. And a second selector for outputting the selected first or second divided clock.