JP3105584B2 - Serial / parallel signal conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial / parallel signal conversion circuit for separating a plurality of serial data signals and converting them into a plurality of parallel data signal strings.

[0002]

2. Description of the Related Art Conventionally, as shown in the signal format of FIG.
When the data signals a1, b1, and c1 are composed of one block and a plurality of bits, the serial input data S1 is divided into a1, b1, and c1 (the next data is a2, b1, and c2).
FIG. 4 shows a conventional circuit for converting parallel output data consisting of b2 and c2). In the conventional example of FIG. 4, three storage circuits 11, 12, and 13 corresponding to three data signals a1, b1, and c1 (next data are a2, b2, and c2) and a reference frame signal S8 are input. Write control signals S9-0, S9-1, S for the storage circuits 11, 12, 13 respectively
9-3 and a signal generator 14 that generates read control signals that are simultaneously read from the three storage circuits 11, 12, and 13 in parallel.

Next, the operation of the conventional example will be described with reference to the timing chart of FIG. First, the write control signals S9-0, S9-1, S9 shifted by one block corresponding to the storage circuits 11, 12, 13 based on the reference frame signal S8.
-2 is generated. The storage circuits 11 to 13 store serial input data S1 and write control signals S9-0 and S9, respectively.
-1, S9-2 and input data a1, a2..., Data b1, b2.
Write data c1, c2... Next, as for the parallel output data S5, S6, and S7, the read control signal S10 is supplied in parallel to the storage circuits 11, 12, and 13 after a lapse of a predetermined number of bits after writing from the write control signal S9-2, and the output data S5 to S7 The data c2, b2, and a2 are output in parallel as the next data series of the data c1, b1, and a1.

[0004]

In the above-described conventional serial / parallel conversion circuit, the number of write control signals generated by the signal generator is required to be equal to the number of output data signals. Since one storage circuit is required for each signal, when the input data signal is separated into many data signals, the control of the storage circuit by the signal generator becomes complicated, and the number of storage circuits is reduced. The disadvantage is that it increases.

[0005]

The serial-to-parallel conversion circuit of the present invention comprises N (N is an integer of 2 or more) blocks.
A memory circuit, each having N pieces individually and an output port for reading an input port for writing the serial input data signal with a data signal to the reference frame including the in one of the input ports of the memory circuit A write control signal for writing a serial data signal, a read control signal for reading data signals written to the storage circuit in parallel from N output ports, and a plurality of parallel output data signals output from the storage circuit. A signal generator for generating a selection signal for selecting a necessary part from the outside based on the reference frame signal input from the outside, and a parallel output data signal output from the storage circuit based on the selection signal. and a selection circuit for outputting Te Shi
In the real / parallel conversion circuit, the storage circuit includes:
1st to Nth input corresponding to the number of blocks
Input port and output port and the first input port
Input means for inputting the serial input data signal from
Connect first output port to second input port
Thereafter, the (N-1) th output port is sequentially set to the Nth input port.
Connection means for connecting to the power port,
When reading data from an output port,
1 block later than the input port data for
It is characterized by protruding.

[0006]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of this embodiment.

The embodiment shown in FIG. 1 is a dual-port type storage circuit 1 having a plurality of ports A, B and C for inputting an input data signal S1 and a plurality of ports D, E and F for outputting data signals. These are written by a write control signal S9 and a read control signal S10 input from the signal generator 3 to write a plurality of data signals,
Reading is enabled. In addition, the storage circuit 1
The read data signal output from the selector circuit 2 selects a necessary part by the selection circuit 2 according to a selection signal S11 generated from the signal generator 3, and becomes an output data signal. A serial input data signal S1 is written from the input port A of the storage circuit 1 for each block by a write control signal S9 generated by the signal generator 3 based on the reference signal S8. When the writing of a1 of the serial data signal S1 is completed, the writing of b1 is performed continuously, and at the same time, the read / write control signals S9 to 1 generated by the signal generator 3 based on the reference signal S8 from the output port D of the storage circuit 1. The reading of a1 is performed by the control signal S10 that has been block-shifted, and then the reading of b1 is performed. The read data signal S2 is input to the selection circuit 2 and the input port B of the storage circuit 1, and is written to the storage circuit 1. That is, when b1 is being written from the input port A to the storage circuit 1, a1 is written from the input port B one block before. By repeating the above, the read data signals S2, S3, and S4 from the storage circuit 1 are output with a shift of one block as shown in FIG. The read data signals S2, S3, and S4 output from the storage circuit 1 are input to the selection circuit 2, and the read data signals S2, S3, and S4 are generated by the selection signal S11 generated by the signal generator 3 based on the reference signal S8. When a1, b1, c, and 1 are completed, the output data signals S5, S6, and S7 are output from the selection circuit 2 in a burst. That is, the parallel data signal a
1, b1 and c1 are extracted and the parallel data signals a2, b2 and c2 are extracted in the next cycle.
After performing an operation of confirming that the pulse specifying the third c1 to be written in 1 is synchronized, the selection signal S1
Send 1

[0008]

As described above, the present invention includes one dual-port type storage circuit, an improved signal generator, and a selection circuit to provide one control signal for controlling the writing of the storage circuit. In addition, since the output data selection circuit can be constituted by a simple circuit such as a gate, the circuit scale can be simplified even if the output data signal increases.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a time chart for explaining the embodiment.

FIG. 3 is a signal format of input data common to the present invention and a conventional example.

FIG. 4 is a block diagram of a conventional serial / parallel signal conversion circuit.

FIG. 5 is a time chart illustrating a conventional example.

[Explanation of symbols]

 1,11-13 storage circuit 2 selection circuit 3,14 signal generator

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-128818 (JP, A) JP-A-2-281818 (JP, A) JP-A-2-234516 (JP, A) 201539 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 5/00 G06F 13/00 353 H03M 9/00

Claims (1)

(57) [Claims] 1. N blocks (N is an integer of 2 or more)
A memory circuit, each having N pieces individually and an output port for reading an input port for writing the serial input data signal with a data signal to the reference frame including the serial to one input port of the memory circuit A write control signal for writing a data signal, a read control signal for reading the data signal written to the storage circuit in parallel from N output ports, and a parallel output data signal for a plurality of columns output from the storage circuit. A signal generator that generates a selection signal for selecting a necessary part from the externally input reference frame signal, and a parallel output data signal output from the storage circuit based on the selection signal. sheet that includes a selection circuit for outputting
In the real-to-parallel conversion circuit, the storage circuit may include a first memory corresponding to the number of blocks.
From the Nth input port and the output port, and from the first input port to the serial input data signal.
Input means for inputting a signal and connecting the first output port to the second input port
Thereafter, the (N-1) th output port is sequentially set to the Nth input port.
Connection means for connecting to the output port, and when reading data from the output port of the storage circuit,
One block from input port data for that output port
A serial / parallel signal conversion circuit characterized in that data is read with a delay of a clock .