JPH04293391A - Time slot conversion circuit - Google Patents

Abstract

PURPOSE:To simplify peripheral hardware performing time slot conversion by providing a delay circuit delaying multiplex data trains, an AND circuit sampling the output of the dealy circuit with a pulse and an OR circuit 0Ring the output of the AND circuit. CONSTITUTION:Multiplexed data 11 whose one time slot is discretely multiplexed in plural information sources (four sources in the figure) of m-bit, are inputted to an AND circuit 4 and a delay circuit 1. Delay circuits 1 to 3 respectively output the inputted multiplexed data while delaying them by (mXn)-bit (N=8 in the figure). AND circuits 4 to 7 obtain the AND between a clock 15 having (mXn/2)-bit and multiplexed data 11 to 14 and output them.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time slot conversion circuit for communication equipment, and more particularly to a time slot conversion circuit for recombining multiplexed data from a plurality of signal sources for each information source.

0002

2. Description of the Related Art FIG. 3 is a block diagram of a line of conventional time slot conversion circuits, and FIG. 4 is a timing diagram for explaining the operation of the conventional example.

RAM for temporarily storing multiplexed data 303
301 is the write address 3 selected by the selection circuit 302.
06 or read address 307 is the address line 305
Input by R by write address 306
The multiplexed data 303 stored in the AM 301 is outputted as multiplexed data 304 that is centrally arranged according to the read address.

[0004] The input multiplexed data 303 is composed of m bits per time slot as shown in FIG.
Four pieces, 1-0, 2-0, and 3-0, are multiplexed in a distributed manner.

When writing this multiplexed data 303 to the RAM 301, the write address 306 is controlled so that the lower address is updated for the same information source, and the upper address is updated for different information sources. The converted data 303 is sequentially written in m-bit units to predetermined memory addresses. On the other hand, the read side sets the read address 307 to 0.
Multiplexed data 304 in a concentrated arrangement is obtained by controlling the data to be updated sequentially starting from the number and reading each piece of information from a predetermined memory address.

[0006]

Since the above-described conventional time slot conversion circuit uses a RAM as a temporary memory, the amount of hardware for peripheral circuits other than the RAM is relatively large. That is, a write and read address generator and a write and read control signal generator are required to drive the RAM. Therefore, when the capacity for converting time slots is relatively small due to the number of information sources in multiplexed data, the RAM format requires a large amount of hardware and is not economical.

[0007]

[Means for Solving the Problem] The present invention has n time slot conversion circuits arranged in a distributed manner (n is a positive integer).
In a time slot conversion circuit that converts, centrally arranges, and outputs a multiplexed data string consisting of information sources, n- delay circuits connected in series delay the multiplexed data; It has n AND circuits that calculate a logical product between the outputs of the AND circuits and a common pulse, and an OR circuit that calculates a logical sum using the outputs of the AND circuits.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a timing diagram for explaining the operation of this embodiment.

Multiplexed data 11 that has been distributed and multiplexed using a plurality of information sources (four in the figure) each having m bits per time slot is input to an AND circuit 4 and a delay circuit 1 . Delay circuits 1 to 3 delay input multiplexed data 11 by m×N (N=8 in the figure) bits and output the delayed data, respectively. AND
The circuits 4 to 7 calculate the logical product of the m×N/2 bit cycle clock 15 and the multiplexed data 11 to 14 and output the result. The OR circuit 8 calculates the logical sum of the outputs from the AND circuits 4 to 7 and outputs it as multiplexed data 16 that has been intensively converted.

[0010] In this way, the number of information sources of the multiplexed data string is n-1 delay circuits, n AND circuits, and 1
The time slots of the multiplexed data string can be converted using the OR circuits.

[0011]

As explained above, the present invention has a delay circuit that delays a multiplexed data string, an AND circuit that samples the output of the delay circuit with pulses, and an OR circuit that ORs the output of the AND circuit. This has the effect of simplifying peripheral hardware that performs time slot conversion.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of this embodiment.

FIG. 3 is a block diagram of an example of a conventional time slot conversion circuit.

FIG. 4 is a timing diagram for explaining the operation of the conventional example.

[Explanation of symbols]

1 to 3 Delay circuit 4-7 AND circuit 8 OR circuit

Claims (1)

[Claims] 1. A time slot conversion circuit that converts a multiplexed data string consisting of n information sources (n is a positive integer) distributed in a distributed manner, centrally arranges and outputs the multiplexed data. n- delay circuits connected in series that delay the output, n AND circuits that calculate a logical product between the output of each of the delay circuits and a common pulse, and a logical sum of the output of each of the AND circuits. A time slot conversion circuit comprising an OR circuit.