JP3003328B2 - Clock signal circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal circuit, and more particularly to a clock signal selection circuit for supplying a plurality of clock signals to a plurality of functional blocks.

[0002]

2. Description of the Related Art A microcomputer has functional blocks such as a timer / counter unit and a communication unit for performing operations based on a predetermined clock signal.
The functional block has required a plurality of clock signals having different frequencies in order to expand the application range.

Conventionally, this kind of clock signal selection circuit has
The circuit configuration was as shown in FIG.

In FIG. 5, a clock signal CK input from the outside is input to a six-stage frequency dividing circuit 29. The six-stage frequency dividing circuit 29 divides the frequency of the clock signal CK and outputs a signal after the frequency division.

When the frequency of the clock signal CK is fx, the divided outputs a, b, c, d, e, and f are fx
/ 2, fx / 4, fx / 8, fx / 16, fx / 32,
The clock signal has a frequency of fx / 64. The frequency-divided outputs a, b, c, d, e, and f are output from the clock signal transfer circuit 28.
Output from the function block 30 and the function block 3
3 is wired.

A mode register H: 32 is a register for setting which of the frequency-divided outputs a, b, c, d, e, and f is to be output to the clock output CKOUT1, and in this case, six types of divided outputs are provided. In order to select the cycle output, a 3-bit register is required. The selector D: 31 divides the frequency-divided outputs a, according to the data set in the mode register H: 32.
One of b, c, d, e, and f is selected and output as a clock output CKOUT1. Table 1 shows the setting values of the mode register H: 26 and the clock output CKOUT1.
1 shows an example of the frequency division output.

[0007]

In this example, when "101" is set in the mode register H: 26, the frequency-divided output d is output to the clock output CKOUT1.

Similarly, CKOUT2 outputs frequency-divided outputs a, b, c, and C in accordance with the value set in mode register I.
One of d, e, and f is output.

FIG. 6 is a circuit example of the selector D: 31 in FIG. In this case, since only one of the six types of signals is selected and output, six AND gates 39 to 44 and
It is composed of three OR gates 36-38.

When "101" is set in the mode register H: 48, the AND gate 41 is selected and the divided output d is set to AN.
CKOUT through D gate 41 and OR gates 37 and 36
1 is output.

FIG. 7 shows an example of an operation timing chart. This timing chart shows the clock output CKOU
This is an operation example in the case where the divided output d is selected and output as the clock output CKOUT2 at T1.

[0013]

Means for Solving the Problems A clock signal circuit according to the present invention is connected to a frequency divider for generating a plurality of frequency-divided signals by inputting a clock signal, a mode register, and a mode register and a frequency divider. A clock signal circuit comprising: a first selector; and a first divided signal group of the plurality of divided signals in response to a signal of the first divided signal group of the plurality of divided signals. Further comprises a second selector for outputting a signal of a different second frequency-divided signal group at its output end as a time-division clock signal in a time-division manner, wherein the first selector receives the time-division clock signal, A latch circuit for latching a signal value of the time-division clock signal output to the output terminal in response to a latch clock signal generated based on the data set in the frequency register group and the mode register. And butterflies.

[0014]

Preferably, further, a first storage circuit for designating one of the timings by the timing signal, and a time division from the clock signal generation circuit in synchronization with the timing designated by the storage circuit. A second storage circuit for storing the frequency-divided signal.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. The clock signal CK input from the outside is input to the six-stage frequency dividing circuit 1. The operation of the six-stage frequency dividing circuit 1 is the same as that of the conventional example described above, and the frequency of the clock signal CK is set to f
When x is set, the frequencies of the divided outputs a, b, c, d, e, and f are fx / 2, fx / 4, fx / 8, and fx / 1, respectively.
6, fx / 32 and fx / 64. Divided outputs a, b,
c, d, e, and f are input to the selector A: 3.

The selector A: 3 divides the selection signal into frequency-divided outputs a,
b, and the divided outputs c, d,
One of e and f is selected and output as a time-division clock signal g. Table 2 shows an example of the values of the divided outputs a and b and the divided output output to the time-division clock signal g. In this example, when the values of the divided outputs a and b are "1" and "0", the divided output d is output as the time-division clock signal g.

[0019]

The divided outputs a and b and the time-division clock signal g
Are output from the clock signal generation circuit 1 and wired to the functional blocks 4 and 7.

The mode register H: 6 has a clock output C
Of the divided outputs a, b, c, d, e, and f to KOUT1,
This is a register for setting which output is to be output. In this case, a 3-bit register is required to select six types of frequency-divided outputs.

The selector B: 5, according to the data set in the mode register H: 6, divides the outputs a, b, c, d,
e or f is selected and the clock output CKO is selected.
Output as UT1. Table 1 shows that the mode register H: 6
And an example of the frequency division output output to the clock output CKOUT1. In this example, the mode register H:
6 when “101” is set, the clock output CKOUT
1, a frequency division output d is output.

Similarly, CKOUT2 outputs frequency-divided outputs a, b, and に 従 い in accordance with the value set in mode register I: 9.
Any one of c, d, e, and f is output.

FIG. 2 is a circuit example of the selector A: 3 in FIG. When the values of the divided outputs a and b are "0, 0", the divided output c is selected, and the signal value of the divided output c is set to the AND gate 1
2 and an OR gate 16 to output a time-division clock signal g. Similarly, the values of the divided outputs a and b are “0, 1”,
In the case of “1, 0” and “1, 1”, the divided outputs d,
e and f are selected and AND gates 13, 14, 15 are ORed
The signal values of the divided outputs d, e, and f pass through the gate 16 and are output as the time-division clock signal g.

FIG. 4 shows an operation timing chart of the above-described embodiment circuit.

FIG. 3 is a circuit example of the selector B: 5 in FIG.

When the set value of the mode register H: 27 is "00"
When it is "0", the frequency-divided output a is selected, and the signal value of the frequency-divided output a passes through the AND gate 23 and the OR gate 22, and CK
Output to OUT1. Similarly, mode register H: 2
When the set value of 7 is "001", the frequency-divided output b is selected, and the signal value of the frequency-divided signal b is output to CKOUT1 through the AND gate 24 and the OR gate 22.

When the set value of the mode register H: 27 is "10"
When "1", the divided output d is selected.When the signal values of the divided outputs a and b are "1, 0", the EXNORs 19 and 20 each become "1" and the output value of the AND gate 18 becomes "1". 1 ". Since the output signal of the AND gate 18 is the latch clock signal h of the latch 17, the latch 17 captures the signal value of the time-division clock signal g.
When the signal value of b changes from “1, 0”, the signal value of the latch clock signal h becomes “0”, and the latch 17 enters the holding state. At this time, the signal value held is the signal value of the frequency-divided output d.
The signal value of the divided output d is output to CKOUT1 through the R gate 22. FIG. 4 shows a timing chart of the operation described above.

Although CKOUT1 is out of phase with respect to the divided output d, it has the same clock signal as the frequency (period).

[0030]

As described above, according to the present invention, a divided output signal can be supplied to each functional block with a smaller number of wires by transferring the divided output signal in a time-division manner.
When an LSI is used, there is an effect that the wiring area can be reduced and the chip area can be reduced.

In this embodiment, an example of a clock signal transfer circuit for transferring six clock outputs by three signal lines has been described. However, this effect is more remarkable as the number of clock outputs increases. .

Table 3 shows a correspondence table between the number of conventional clock output wirings and the number of wirings when the present invention is implemented. n is 2
In the case of the above integer, the conventional n + 2 ^n-1 lines to n + 2
ⁿ wirings can be wired in the number of wires (n + 1) by using the present invention.

[0033]

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a clock signal selection circuit of the present invention.

FIG. 2 is a circuit configuration diagram of a selector A: 3 in FIG.

FIG. 3 is a circuit configuration diagram of a selector B: 5 in FIG. 1;

FIG. 4 is an example of an operation timing chart of FIGS. 1 and 3;

FIG. 5 is a circuit configuration diagram of a conventional clock signal selection circuit.

FIG. 6 is a circuit configuration diagram of a selector D: 31 in FIG. 5;

FIG. 7 is an example of an operation timing chart of FIG. 5;

[Explanation of symbols]

1,28 clock signal generation circuit 2,296 6-stage frequency divider 3,5,8,31,34 selector circuit 4,7,30,33 function block 6,9,27,32,35,48 mode register 10, 11,25,26,45,46,47 Inverters 12,13,14,15,18,21,23,24,3
9, 40, 41, 42, 43, 44 AND gate 16, 22, 36, 37, 38 OR gate 17 Latch circuit 19, 20 EXNOR gate

Claims (3)

(57) [Claims] 1. A clock signal circuit comprising: a frequency divider for receiving a clock signal to generate a plurality of frequency-divided signals; a mode register; and a first selector connected to the mode register and the frequency divider. A second frequency division different from the first frequency division signal group among the plurality of frequency division signals in response to a signal of a first frequency division signal group of the plurality of frequency division signals A second selector for outputting the signal of the signal group in a time-division manner as a time-division clock signal at an output end thereof, wherein the first selector receives the time-division clock signal and receives the first divided signal group; And a latch circuit that latches a signal value of the time-division clock signal output to the output terminal in response to a latch clock signal generated based on data set in the mode register. The clock signal circuit for the butterflies. 2. The mode register includes first and second data bits, and the first selector receives a signal value latched by the latch circuit and a signal of the first frequency-divided signal group. , The value of the first data bit is the first
Output of one of the first frequency-divided signal groups in response to the value of the second data bit, prohibiting the output of the latched signal value when the logical value of And a logic gate for inhibiting the output of the signal of the first frequency-divided signal group and outputting the latched signal value when the value of the data bit indicates the second logical value. A clock signal circuit as described. 3. The first frequency division group includes first and second frequency division groups.
, And the mode register has first, second,
And the third bit, wherein the first selector generates the latch clock signal that is active for a predetermined period in response to the second and third bits and the first and second divided signals. A first logic circuit, a first AND gate receiving the first frequency-divided signal, an inverted value of data stored in the first bit, and an inverted value of data stored in a third bit; A second AND gate receiving the second frequency-divided signal, the inverted value of the data stored in the first bit, and the data stored in the third bit; A third AND gate that receives the signal value and the data stored in the first bit, and an OR gate that receives the outputs of the first, second, and third AND gates. The clock according to claim 1 Signal circuit.