JPH08329671A - Semiconductor delaying device - Google Patents

Abstract

PURPOSE: To expand versatility in signal processing by adding a function of an inversion delay as well as a normal rotation delay. CONSTITUTION: In addition to a memory cell part 2, read address generation part 1 and write address generation part 3, this device is provided with a selector part 4 and a normal rotation/inversion changeover control block 5, and normal rotation/inversion changeover signals 7, 8 and 9 are inputted to the selector part 4 and the normal rotation/inversion changeover control block 5. Consequently, the read/write operation to (n) pieces of memory cells (21 -2n ) is constituted so as to be capable of being changed over to a first mode repeating as 21 →22 →...→2n →21 →22 →...→2n or to a second mode repeating as 21 →22 →...→2n →2n →-2n-1 →...→21 →22 →....

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor delay device used for signal processing.

[0002]

2. Description of the Related Art A conventional semiconductor delay device will be described below. FIG. 3 shows a circuit diagram of a conventional semiconductor delay device.
In FIG. 3, reference numeral 32 is a memory cell section. Reference numeral 31 is a read address generator. 33 is a write address generation unit. The read address generation unit 31 and the write address generation unit 33 are each configured by a D latch, and each of the D latches 31 ₁ , 33 ₁ , 31 ₂ , 33 ₂ , ...
Connect each Q output to each D input in the order of 1 _n and 33 _n , and connect the Q output of the last D latch 33 _n to the D of the first D latch 31 ₁ .
Connected to the input and so on. Only the D latch 33 _n is a D latch with a set, and the others are D latches with a reset. The memory cell unit 32 includes n (n is an integer) memory cells 32 ₁ , 32 ₂ , ..., 32 _n.
Are arranged in a line. 34 is a reset input terminal for inputting a reset signal, 35 is a clock input terminal for inputting a common clock signal, 36 is a time series signal input terminal,
37 is a time series signal output terminal.

The operation of the semiconductor delay device configured as described above will be described below. First, when a reset signal is input from the reset input terminal 34, the D latch 3
The output Q of only 3 _n is set to “H”, and the other D latches 31 ₁ , 33 ₁ , 31 ₂ , 33 _{2 to} 31 _n are set to “L” by the reset operation. When the first clock signal is input from the clock input terminal 35 in this state, D
The output Q of the latch 31 ₁ becomes "H", and the D latch 33 _n
Output Q becomes "L". At this time, the D latch 31
_{By 1} output Q becomes "H" 1 th memory cell 32 ₁ performs a read operation, and outputs to the sequence signal output terminal 37 when the signal of the memory cell 32 ₁ from the data output terminal O.

Next, when the second clock signal is input from the clock input terminal 35, the output Q of the D latch 33 ₁ becomes "H" and the output Q of the D latch 31 ₁ becomes "L". When the output Q of the D latch 33 ₁ becomes “H”, the memory cell 32 ₁ performs the write operation, and the time series input signal input from the time series signal input terminal 36 is stored in the data input terminal I for one clock. Write to cell 32 ₁ .

Similarly, each time a clock signal is input from the clock input terminal 35, the state of "H" shifts to D latch 31 ₂ → 33 ₂ → ... → 31 _n → 33 _n , The memory cells 32 ₂ , 32 _{3 to} 32 _n-1 , 32 _n perform a read / write operation, and when a clock signal is further input, the D latch 31 ₁ is again in the “H” state and the memory cell 32 ₁ Read operation is performed, and the same operation is repeated thereafter.

In this way, the memory cells 31 ₁ , 32 ₂ ,
By repeating the read / write operations of 32 _{3 to} 32 _n-1 and 32 _{n in} a loop, the signals input in time series to the time series signal input terminal 36 become signals delayed by 2n clock periods. It is output from the series signal output terminal 37.

[0007]

However, in the above-mentioned conventional configuration, only the forward delay operation (so-called first-in first-out operation) of delaying the time-series input signals and outputting them in the same order as the input order can be performed. It was not possible to perform the inverting delay operation (so-called first-in first-out operation) of delaying the series input signal and outputting it in the reverse order of the input order.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor delay circuit having both functions of a normal rotation delay operation and an inversion delay operation.

[0009]

According to another aspect of the present invention, there is provided a semiconductor delay device comprising a plurality of memory cells arranged in a row from a first number to a last number, in which data input terminals and data output terminals are commonly connected. Section and the memory cells of the memory cell section are arranged in a row from the first to the last and arranged with a common clock as an input, and a Q output is supplied to each memory cell of the memory cell section as a read signal. A read address generation unit including a plurality of D latches, and a D address latch of each of the read address generation units arranged in a row from the first to the last number corresponding to each memory cell of the memory cell unit and receiving a common clock Q of
Corresponding to the write address generation unit composed of a plurality of D latches for supplying the outputs as the D inputs and supplying the Q output as the write signal to each memory cell of the memory cell unit, and corresponding to each memory cell of the memory cell unit. First
A selector section including a plurality of selectors arranged in a row from the numbered to the last to select the source of the D input to each D latch of the read address generation section from the Q outputs of the plurality of D latches of the write address generation section, A selection control unit for selecting a supply destination of the Q output of the last D latch of the write address generation unit from the D inputs of the plurality of D latches of the read address generation unit, and the selection control unit is configured to store the memory cells in the first mode. In order to repeat the read / write operation of each memory cell of each unit in the direction from the first to the last, the supply destination of the Q output of the last D latch of the write address generation unit is set to a plurality of Ds of the read address generation unit. In the second mode, the read / write operation of each memory cell in the memory cell section is selected from the D input of the latch and the direction from the first to the last and the operation from the last to the last. D of a plurality of D latches supply destination read address generator of the Q output of the last number of the D-latch of the write address generator so as to repeat alternately the direction of the turn
Each selector of the selector unit selects from the input, and each selector of the selector unit repeats the read / write operation of each memory cell of the memory cell unit only in the first to last direction in the first mode. The source of the D input to the D latch is selected from the Q outputs of the plurality of D latches of the write address generation unit, and the read / write operation of each memory cell of the memory cell unit is performed from the first to the last in the second mode. Source and the source of the D input to each D latch of the read address generating unit are alternately repeated in the direction from the last number to the first direction.
The Q output of the latch is selected.

According to another aspect of the semiconductor delay device of the present invention, a memory cell portion having a plurality of memory cells arranged in a row from the first to the last and commonly connecting a data input terminal and a data output terminal, and a memory cell portion. Corresponding to each memory cell of No. 1 to the last, arranged in a row and composed of a plurality of D latches which receive a common clock as an input and supply a Q output as a read signal to each memory cell of the memory cell section. The Q address of each D latch of the read address generating section and the D cell of the memory cell section are arranged in a line from the first to the last and arranged in a row, and the common clock is input to the D output of each D latch.
A plurality of D's that are input and supply the Q output to each memory cell of the memory cell section as a write signal.
Write source of D input to each D latch of the read address generator arranged in a row from the first address to the last address corresponding to each memory cell of the memory cell unit A selector section composed of a plurality of selectors selected from the Q outputs of a plurality of D latches of the address generation section, and the last D of the write address generation section.
And a selection control unit that selects the supply destination of the Q output of the latch from the D inputs of the plurality of D latches of the read address generation unit, and the selection control unit supplies the Q output of the last D latch of the write address generation unit. First, in the first mode, the read address generating unit is provided via the first selector of the selector unit so that the read / write operation of each memory cell of the memory cell unit is repeated only from the first to the last direction. The D input of the 1st D latch of is selected, and in the second mode, reading / reading of each memory cell of the memory cell section is performed.
The first read address generation unit is operated through the first selector of the selector unit so that the write operation is alternately repeated in the first to last direction and the last to first direction.
The state of selecting the D input of the No. D latch and the state of selecting the D input of the final D latch of the read address generating unit via the final selector of the selector unit are switched to each other. The selector is the first source of the D input to the first D latch of the read address generator.
In the mode, the Q output of the last D latch of the write address generation unit is set via the selection control unit so that the read / write operation of each memory cell of the memory cell unit is repeated only from the first to the last direction. In the selected mode, the write address generation unit is configured to alternately repeat the read / write operation of each memory cell in the memory cell unit in the first to final direction and in the final to first direction. Of the first D-latch of the selector unit and the state of selecting the Q-output of the second D-latch of the write address generator are switched, and the selectors from the second to the last one are selected. The selectors of the respective numbers up to the numbers of (1) to (3) are used as the source of the D input to the D latches of the respective numbers from the second number to the number immediately before the last number of the read address generator, and in the first mode, Reading of each memory cell of the parts,
In order to repeat the write operation only in the direction from the first number to the last number, the Q output of the D latch of each number from the first number to the number immediately before the last number of the write address generator is selected, In the 2 mode, the read / write operation of each memory cell of the memory cell section is alternately repeated from the first to the last direction and from the last to the first direction in the write address generating section. To the last two numbers before the last D latch, the Q outputs of the respective D latches are selected, and the third to the last D write latch Q outputs of the write address generator are selected. Switch between states and the last selector in the selector section
As a source of the D input to the last D latch of the read address generation unit, the read / write operation of each memory cell of the memory cell unit is repeated only in the first to last direction in the first mode. , The Q output of the D latch of the number immediately preceding the last number of the write address generating section is selected, and in the second mode, the read / write operation of each memory cell of the memory cell section is performed from the first number to the last number. And the write address generation via the selection control unit and the state of selecting the Q output of the D latch of the number immediately preceding the final number of the write address generation unit so as to be repeated alternately in the direction from the last number to the first number. The Q output of the last D latch in the section is switched to the selected state.

A semiconductor delay device according to a third aspect is the semiconductor delay device according to the first or second aspect, in which the first D latch of the read address generator has a set input, and the read address generator has a set input. The D-latch of each number from the second to the last and the D-latch of each number from the first to the last of the write address generator have a reset input, and the first latch of the read address generator at the time of start-up. At the same time as setting the D latch,
The D latch of each number from the number to the last number and the D latch of each number from the first number to the last number of the write address generator are reset.

[0012]

According to the structure of the present invention, the read / write operation of each memory cell of the memory cell section is performed in the first mode by the selection operation of the selector section and the selection control section.
The forward rotation delay is repeated only in the direction from the number to the final number,
In the second mode, an inversion delay is performed in which the read / write operation of each memory cell of the memory cell section is alternately repeated in the first to final direction and in the final to first direction.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the semiconductor delay device of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a semiconductor delay device according to an embodiment of the present invention.
In FIG. 1, the memory cell unit 2 includes a plurality of memory cells 2 ₁ , 2 arranged in a line from the first to the last (n).
₂ , ..., 2 _n−1 , 2 _n , the data input terminal I and the data output terminal O are commonly connected, the data input terminal I is connected to the time-series signal input terminal 10, and the data output terminal O is It is connected to the series signal output terminal 11.
In this case, when the read control signal of "H" is input to the read control signal input terminal R, the memory cells 2 ₁ , 2 ₂ to 2 _n-1 and 2 _n read data to the data output terminal O. When a write control signal of “H” is input to the write control signal input terminal W, data is written from the data input terminal I.

The read address generator 1 is a memory cell
Each memory cell 2 of part 2₁, 2₂,…, 2_n-1, 2_n
Corresponding to, the 1st to the last number (nth) are arranged in a line
Multiple D-latch 1₁, 1₂, ..., 1_n-1, 1_nFrom
Become. This D latch 1 ₁, 1₂, ..., 1_n-1, 1
_nIs a common clock input from the clock input terminal 6.
Input to the memory and Q output to each memory of the memory cell section 2.
Cell 2₁, 2₂,…, 2_n-1, 2_nRead control signal
The read control signals are supplied to the input terminals R, respectively.
It

In this case, the D latch 1 ₁ has a set (S), and the D latches 1 ₂ , ..., 1 _n-1 and 1 _n have a reset (R), and these are common to the reset input terminal 12. When the reset signal of "H" is input to the reset input terminal 12, the D latch 1 ₁ is set and the Q output becomes "H", and the D latch 1 ₂ , ..., 1 _n-1 ,
1 _n is reset and the Q output becomes "L".

The write address generator 3 is a memory cell
Each memory cell 2 of part 2₁, 2₂,…, 2_n-1, 2_n
Corresponding to, the 1st to the last number (nth) are arranged in a line
Multiple D-latch 3₁, 3₂,…, 3_n-1, 3_nFrom
Become. This plurality of D latches 3 ₁, 3₂,…, 3_n-1, 3
_nIs a common clock input from the clock input terminal 6.
Input to the D address of the read address generator 1.
Touch 1₁, 1₂, ..., 1_n-1, 1_nQ output of each
D input and Q output of each memory cell unit 2
Memory cell 2₁, 2₂,…, 2_n-1, 2_nWriting
As a write control signal to the control signal input terminal W, respectively.
Supply. That is, D latch 3₁ , 3₂,…, 3_n-1 ,
Three_nD input corresponds to the read address generator 1
D latch 1₁ , 1₂ ~ 1_n-1 , 1_nConnected to the Q output of
ing. Also, the first D-latch 3₁ Q output of
Kuta 4₁B input and selector 4₂Connected to the A input of
Have been. The last (n) D latch 3_nQ output of
Selector 4_n-1To the B input of and the D input of the selection control unit 5.
It is connected. 2nd D-latch 3₂ From the (n-
1) No. D latch 3_n-1 Q outputs of the
1) No. {k is 2, ..., (n-1)} selector 4₂,
…, 4_n-1A input and k-1th selector 4₁,
…, 4_n-2Connected to the B input of.

In this case, the D latches 3 ₁ , 3 ₂ , ..., 3
_{All of n-1} and _3n have a reset function, and they are commonly connected to the reset input terminal 12. When the "H" reset signal is input to the reset input terminal 12, the D latches 3 ₁ , 3 ₂ , ..., 3 _n-1 , 3 _n are reset and Q
The output becomes "L". The selector unit 4 includes the memory cell unit 2
, 2 _n-1 , 2 _n corresponding to the respective memory cells 2 ₁ , 2 ₂ , ..., 2 _n-1 , 2 _n , a plurality of selectors 4 ₁ , 4 ₂ , ... , 4 _n . The plurality of selectors _{4 1, 4 2, ...,} 4 n is the read address generation unit and each of the D latches ₁ 1 1, 1 _2, ..., 1 _n-1,
The source of the D input to 1 _n is selected from any two or three Q outputs of the plurality of D latches 3 ₁ , 3 ₂ , ..., 3 _n-1 , 3 _n of the write address generator 3. That is, the selector _{4 1, 4 2 ~4 n-} 1, 4 n output Q of, D latches ₁ 1 of the read address generator 1, respectively, 1 _2-1
It is connected to the D inputs of _n-1 , 1 _n .

In this case, each of the selectors 4 ₁ , 4 ₂ , ..., 4 _n of the selector section 4 reads out a plurality of memory cells 2 ₁ , 2 ₂ , ..., 2 _n-1 , 2 _n in the first mode. .D-latch 1 ₁ of each read address generator 1 so that the write operation is repeated only from the first to the last direction
The source of the D input to 1 ₂ , ..., 1 _n-1 , 1 _n is the plurality of D latches 3 ₁ , 3 ₂ , ..., 3 of the write address generator 3.
Either _n-1 or 3 _n is selected from two or three Q outputs. In the second mode, the read / write operations of the plurality of memory cells 2 ₁ , 2 ₂ , ..., 2 _n-1 , 2 _n are performed from the first to the last direction and from the last to the first direction. The source of the D input to each of the D latches 1 ₁ , 1 ₂ , ..., 1 _n-1 , 1 _n of the read address generator 1 is alternately written to the plurality of D latches 3 of the write address generator 3. _1, 3 _2, ..., is selected from 3 _n-1, 3 _n or two to three of Q output.

Specifically, the first part of the selector section 4 will be described.
Number selector 4₁Is a selection signal input for switching between normal rotation and reverse rotation.
S supplied from the force terminals 7 and 8₁Input, S₂Select to input
Depending on the input of the selection signal, A input, B input and Q output
And C input, S₁Input is “L”, S₂
When the input is "L", select the C input and press S₁Input is
"L", S₂When the input is "H", select B input,
S₁When the input is "H", S₂Regardless of input
First, the A input is selected. And input selection signal
S supplied to terminals 7 and 8₁Input, S₂Input selection signal
Appropriately set in the first mode and the second mode
As a result, the first D line of the read address generator 1 is
Touch 1₁As the source of D input to the
Of the write address generator 3 via the selection controller 5.
Last D latch 3_nQ output of is selected. Also, the second
In the mode, the first D of the write address generator 3
Latch 3₁State and write address to select the Q output of
The second D-latch 3 of the generator 3 ₂Condition to select the Q output of
Switch between states.

Also, the selectors 4 ₂ ..., 4 _n-1 of the numbers from the second number to the number immediately before the last number of the selector unit 4 are selected.
Operates to select the A input when the selection signal to the S input supplied from the selection signal input terminal 7 is "H", and the B input when the selection signal is "L". Then, by appropriately setting the selection signal to the S input supplied to the selection signal input terminal 7 in the first mode and the second mode, respectively, the second to last bits of the read address generation unit 1 can be set. In the first mode, as the source of the D input to the D latches 1 ₂ , ..., 1 _n-1 of each number up to the number, from the first number of the write address generating unit 3 to the number two numbers before the last number. , Qn of D latches 3 ₁ , ..., 3 _n-2 are selected. Also,
The second mode, the write address generator D latch 3 ₁ of each number from No. 1 up to two previous number of the last number of 3, ..., state and write address 3 _n-2 of the Q outputs respectively selected No.3 from each number to the last number D-latch 3 ₃ of generator 3, ..., and a state of selecting 3 _n of Q outputs, respectively.

Further, the final selector 4 _n of the selector section 4 has an A input when the selection signal to the S input supplied from the selection signal input terminal 9 for switching the normal rotation / inversion is “H”,
When it is "L", it operates to select the B input. Then, the first selection signal to the S input supplied to the selection signal input terminal 9 is input.
In the first mode, as the source of the D input to the final D latch 1 _n of the read address generator 1, the final address of the write address generator 3 is appropriately set in the first mode and the second mode. The Q output of the D latch 3 _n-1 of the previous number is selected. Further, in the second mode, the state of selecting the Q output of the D latch 3 _{n-1 having} the number immediately before the final number of the write address generation unit 3 and the final state of the write address generation unit 3 via the selection control unit 5. The Q output of the No. D latch 3 _n is switched to the selected state.

The selection control unit 5 supplies the Q output of the last (n) th D latch 3 _n of the write address generation unit 3 to the two D latches 1 ₁ , 1 _{n of the} read address generation unit 1.
Select from D input. That is, the selection control unit 5 connects the D input to the Q output of the D latch 3 _n , connects the Q ₁ output to the B input of the selector 4 _n , and connects the Q ₂ output to the A of the selector 4 ₁ .
Connected to input.

In this case, the selection control unit 5 operates in the first mode.
A plurality of memory cells 2₁, 2₂,…, 2_n-1, 2_n
Read / write operations from the first to the last
Only the last of the write address generator 3 repeats
D latch 3_nRead the output destination of the Q output of
Two D-latch 1 of raw part 1₁, 1_nSelect from D input of
It In the second mode, the plurality of memory cells 2₁,
2₂,…, 2_n-1, 2 _nRead / write operation
Interchange from the 1st to the last direction and from the last to the 1st direction
The last number of the write address generator 3 so as to repeat each other
D latch 3_nRead the output destination of the Q output of
Two D-latch 1 of raw part 1₁, 1_nSelect from D input of
It

To be more specific, the selection controller 5 controls the D
If the input is "L", Q ₁ output, Q ₂ output outputs the "L" regardless of the S input. In the case of the D input is "H", Q ₁ outputs "L" when the selection signal to the S input supplied from the selection signal input terminal 9 is "H", Q ₂ output becomes "H" ( Q ₂ output is selected), when the selection signal to S input is “L”, Q ₁ output is “H”, Q ₂ output is “L”
(Q ₁ output is selected). Then, the first selection signal to the S input supplied to the selection signal input terminal 9 is input.
In the first mode, the first selector 4 of the selector unit 4 serves as a supply destination of the Q output of the last D latch 3 _n of the write address generation unit 3 by appropriately setting the mode and the second mode. selecting D latch 1 ₁ D input of the first number of the read address generator 1 through the _1. Further, in the second mode, the first address of the read address generation unit 1 is passed through the _first selector 4 ₁ of the selector unit 4.
The state of selecting the D input of the second D latch 1 ₁ and the state of selecting the D input of the final D latch 1 _n of the read address generating unit 1 through the final selector 4 _n of the selector unit 4 are switched. .

FIG. 2 is a timing chart of the semiconductor delay device of the embodiment shown in FIG. In FIG. 2, (a) is a timing chart at the time of inversion operation, and (b) is a timing chart at the time of forward rotation operation. In FIG. 2, 22 is the Q output of the D latch 1 _n , 23 is the Q output of the D latch 3 _n ,
24 is the Q ₁ output of the selection control unit 5, 25 is the Q ₂ output of the selection control unit 5, 26 is the clock signal of the clock input terminal 6,
27 is a selection signal of the selection signal input terminal 7, 28 is a selection signal of the selection signal input terminal 8, and 29 is a timing chart of the selection signal of the selection signal input terminal 9.

The selection signals supplied to the selection signal input terminals 7 to 9 are created by a timing generation circuit (not shown). The operation of the semiconductor delay circuit of this embodiment constructed as above will be described below. When a reset signal is input from the reset input terminal 12 at startup,
The set D latch 1 1 of the read address generator ₁ is set and the Q output becomes “H”, and the other D latches 1 ₂ , ..., 1 _n−1 , 1 _n are all in the “L” state by the reset operation. become. At this time, the memory cell 2 ₁ performs the read operation.

The first clock signal is applied to the clock input terminal 6.
Is input (20 in FIG. 2)₁ , 21₁ State), D
Latch 3₁ Q output becomes "H", and the memory cell 2₁ But
Perform a write operation. At this time, the selector 4₁B's
Power, selector 4₂A input of becomes "H". Where
Lectar 4₁Selection signal to₁Input is “L”, S₂Entering
Since the force becomes “L”, its Q output selects C input.
Output "L". Also, selector 4₂Q output of A input
The force is output and the state becomes "H". As a result,
When the lock signal is input from the clock input terminal 6
(20 in FIG. 2₂ , 21 ₂ State) D latch 1₂ Q output
Only becomes "H". At this time, the memory cell 2₂Is read
Then perform the operation. In this way, clock input terminal 6
D latch 1 every time a check signal is input₁, ..., 1_n, 3
₁,…, 3_n"H" state of the output of D latch 1₁ → D
Touch 3₁ → D latch 1₂ → D latch 3₂ → ・ ・ ・ → D
Touch 1_{n- 1} → D latch 3_n-1 → D latch 1_n→ D latch
Three_nMemory cell 2₁ , 2₂ ~ 2_n-1 ,
2_nThe read / write operation is repeated in this order.
As a result, the time series input from the time series signal input terminal 10
The column signals are sequentially stored in memory cell 2 ₁ ,…, 2_nWritten in
It Up to this point, the forward delay and the reverse delay are the same operation.
It The following operation differs depending on the forward rotation delay and the reverse delay.

First, the case of inversion delay will be described.
The clock signal is continuously input from the clock input terminal 6 D
Latch 3_nOutput becomes "H" (Fig. 2 (a)
20 ₃ State) Memory cell 2_nPerforms a write operation.
Also, selector 4_n-1B input and selection control unit 5 input
The force D becomes "H". At this time, the selection signal input terminal 9
The selection signal becomes "L". As a result, Q of the selection control unit 5
₁The output becomes "H". Also, selector 4_nQ output
Selects the B input and outputs "H". Selector 4_n-1
"L" is output because "H" is input to the S input of
Is done. As a result, the next clock signal is input.
And D latch 1_nOutput becomes "H", and memory cell 2
_nRead operation is performed. Next clock signal is input
When pressed (20 in Fig. 2 (a))_Four State), D latch 3
_nOutput becomes "H", and memory cell 2_nIs writing
Do the work. Also, selector 4_n-1B input and selection system
The input D of the control section 5 becomes "H". At this time, select signal input
The selection signal of the terminal 9 becomes "H". As a result, selection control
Part 5 Q₂Output becomes "H", but selector 4₁Q out
The force selects the C input and outputs "L". Also select
Type 4_n-1Since the S input of is changed to "L", the selector 4_n-1
Outputs "H". As a result, the next clock signal
Is input, D latch 1_n-1 Output is "H"
Memory cell 2_{n- 1} Read operation is performed. Next
When the clock signal of is input, the D latch 3 _n-1 Output
Becomes "H", and memory cell 2_n-1 Write operation
U After this, the clock signal is input from the clock input terminal 6.
Memory cell 2 each time it is pressed_n-2→ ・ ・ ・ → 2₂ → 2₁ When
Reading and writing are performed in order. Memory cell 2₁ of
When the writing operation is completed, the time series signal input terminal 1
The time series signals from 1st to nth input from 0 are
Time-series signal with 2n clock delay from the nth to the 1st
Signal is output to the time-series signal output terminal 11. Slow reverse
This is the memory cell 2₁ → 2_nIn order (read
Write), then reverse 2_n→ 2₁ Read in order
Put out / write. Next is 2₁ → 2_nRead in order
By writing and writing, and repeating this operation
Has been realized. Next, the case of the forward rotation delay is explained.
Reveal The clock signal is input from the clock input terminal 6.
Continue to be D latch 3_nWhen the output of H becomes "H" (Fig. 2
21 of (b)₃ State) Memory cell 2_nWrite operation
I do. Also, selector 4_n-1B input and block
The input D of 5 becomes "H". At this time, the selection signal input terminal
The selection signal of the child 9 remains "H". As a result, select
Q of control unit 5₂The output becomes "H". Selector 4₁Q of
The output selects the A input and outputs "H". Selector 4
_n-1Since "H" is input to the S input of, "L"
Is output. As a result, the following clock signal is input.
(21 in FIG. 2B)₃ State), D latch 1₁ of
Output goes to "H", and memory cell 2₁ Read operation
Done. When the next clock signal is input, D
Chi 3₁ Output becomes "H", and memory cell 2₁ Is written
Do only the movement. At this time, the selector 4₁B input of
Selector 4₂A input of becomes "H". Selector 4₁Is
S₁Input is “H”, S₂Since the input becomes “H”,
The Q output selects the A input and outputs "L". In addition,
Lectar 4₂Q output of the A input is output, "H" state
become. As a result, the next clock signal is input from terminal 6.
D-latch 1 when applied₂ Only the Q output of "H"
It At this time, the memory cell 2₂ Performs a read operation. This
After that, the clock signal is input from the clock input terminal 6.
Memory cell 2 every time₃→ ・ ・ ・ → 2_n-1 → 2 _nRead in order
Produce and write. Memory cell 2_nWrite operation
Input from the time-series signal input terminal 10 when
The time series signals from the 1st to the nth are
Time series as time series signals delayed by 2n clocks up to n
It is output to the column signal output terminal 11. This is the forward rotation delay
Sea urchin memory cell 2₁ → 2_nIn order of (reading) writing
See next 2₁ → 2_nRead and write in the order
It is realized by repeating this operation.

[0029]

According to the semiconductor delay device of the present invention, a semiconductor delay device having both functions of a first-in-first-out type forward rotation delay and a first-in-first-out first type inversion delay is provided only by adding a selector section and a selection control section. Can be achieved with a minimum increase in area.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor delay device according to an embodiment of the present invention.

FIG. 2 is a timing chart of a normal / inversion switching signal according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional semiconductor delay circuit.

[Explanation of symbols]

1, 31 read address signal generation unit 2, 32 memory cell unit 3, 33 write address signal generation unit 4 selector unit 5 selection control unit 6, 35 clock input terminal 7 selection signal input terminal 8 selection signal input terminal 9 selection signal input terminal 10, 36 Time-series signal input terminal 11, 37 Time-series signal output terminal 12, 34 Reset input terminal 1 ₁ , 33 _n D latch with set 1 ₂ to 1 _n , 3 _{1 to} 3 _n D latch with reset 2 ₁ to 2 _n memory cells 4 ₁ to 4 _n selectors _{31 1 ~31 n, 33 1 ~33} n-1 with reset of the D-latch 32 ₁ to 32 _n memory cells 20 of the timing chart 21 during reverse operation during forward operation chart

Claims (3)

[Claims] 1. A memory cell section comprising a plurality of memory cells arranged in a row from the first to the last and commonly connecting a data input terminal and a data output terminal, and a memory cell section corresponding to each memory cell. And a read address generating section comprising a plurality of D latches arranged in a line from the first to the last and receiving a common clock as an input and supplying a Q output to each memory cell of the memory cell section as a read signal. Corresponding to each memory cell of the memory cell section, the first to the last cells are arranged in a line and the common clock is used as an input, and the Q output of each D latch of the read address generating section is used as a D input. In addition, a write consisting of a plurality of D latches which respectively supply the Q output to each memory cell of the memory cell section as a write signal. The address generating unit and the source of the D input to each D latch of the read address generating unit are arranged in a line from the first address to the last address corresponding to each memory cell of the memory cell unit and the write address is set to the write address. A selector unit including a plurality of selectors that select from the Q outputs of a plurality of D latches of the generation unit, and a supply destination of the Q output of the last D latch of the write address generation unit to the plurality of D latches of the read address generation unit. And a selection control unit for selecting from the D input of the memory cell unit. The selection control unit repeats the read / write operation of each memory cell of the memory cell unit only in the first to last direction in the first mode. The source of the Q output of the last D latch of the write address generator is selected from the D inputs of the plurality of D latches of the read address generator, and the second mode is selected. At the time of reading, the read / write operation of each memory cell of the memory cell section is alternately repeated in the direction from the first to the last and in the direction from the last to the first. Q of D latch
The output is supplied to a plurality of D's of the read address generator.
Select from the D input of the latch, and each selector of the selector unit repeats the read / write operation of each memory cell of the memory cell unit only in the first to last direction in the first mode. The source of the D input to each D latch of the read address generator is selected from the Q outputs of the plurality of D latches of the write address generator, and the memory cell of each of the memory cell units is read during the second mode. The source of D input to each D latch of the read address generator is generated as the write address so that the write operation is alternately repeated from the first to the last direction and from the last to the first direction. Delay device for selecting from the Q outputs of a plurality of D latches in the same section. 2. A memory cell section comprising a plurality of memory cells arranged in a line from the first to the last and commonly connecting a data input terminal and a data output terminal to each other, and corresponding to each memory cell of the memory cell section. And a read address generating section comprising a plurality of D latches arranged in a line from the first to the last and receiving a common clock as an input and supplying a Q output to each memory cell of the memory cell section as a read signal. Corresponding to each memory cell of the memory cell section, the first to the last cells are arranged in a line and the common clock is used as an input, and the Q output of each D latch of the read address generating section is used as a D input. In addition, a write consisting of a plurality of D latches which respectively supply the Q output to each memory cell of the memory cell section as a write signal. The address generating unit and the source of the D input to each D latch of the read address generating unit are arranged in a line from the first address to the last address corresponding to each memory cell of the memory cell unit and the write address is set to the write address. A selector unit including a plurality of selectors that select from the Q outputs of a plurality of D latches of the generation unit, and a supply destination of the Q output of the last D latch of the write address generation unit to the plurality of D latches of the read address generation unit. Selection control section for selecting from the D input of the memory cell section in the first mode as a supply destination of the Q output of the last D latch of the write address generation section. The read address is read through the first selector of the selector unit so that the cell read / write operation is repeated only from the first to the last direction. When the D input of the first D latch of the generating section is selected and the read / write operation of each memory cell of the memory cell section is selected in the second mode, the read / write operation is performed in the direction from the first to the last and from the last to the first. State of selecting the D input of the first D latch of the read address generating section through the first selector of the selector section and the final selector of the selector section so as to be alternately repeated in the direction of And the state in which the D input of the last D latch of the read address generation unit is selected is switched to the first selector of the selector unit to the first D latch of the read address generation unit. As a source of the D input, the selection control unit is configured to repeat the read / write operation of each memory cell of the memory cell unit only in the first to last direction in the first mode. Q of to D latches of the last number of the write address generator
In the second mode, the output is selected, and the read / write operation of each memory cell of the memory cell section is alternately repeated in the first to final direction and in the final to first direction. The state of selecting the Q output of the first D latch of the write address generating section and the state of selecting the Q output of the second D latch of the write address generating section are switched, and the second number of the selector section is selected. To the last number before the last number, the selectors of the respective numbers from the second number to the last number before the last number of the read address generator are the sources of the D input. In the first mode, the read / write operation of each memory cell of the memory cell unit is repeated only in the direction from the first to the last, so that the first to the last of the write address generators are used. The Q outputs of the D latches of the respective numbers up to the previous number are selected respectively, and in the second mode, the read / write operation of each memory cell of the memory cell section is performed from the first to the last direction and from the last number. A state in which the Q output of the D latch of each number from the first number to the second number before the last number of the write address generator is selected so as to be alternately repeated in the direction of No. 1 and the write address generation. The Q output of the D latch of each number from the third to the last number of the section is switched to the state of selecting the Q output, and the last selector of the selector section outputs to the last D latch of the read address generating section. As a source of the D input, in the first mode, the write operation is performed so that the read / write operation of each memory cell of the memory cell section is repeated only from the first to the last direction. The Q output of the D-latch, which is the last number before the last number of the dress generation section, is selected, and in the second mode, the read / write operation of each memory cell of the memory cell section is changed from the first to the last direction. The write operation is performed via the selection control unit and the state of selecting the Q output of the D latch of the number immediately preceding the final number of the write address generation unit so as to be alternately repeated from the last number to the first direction. A semiconductor delay device adapted to switch between a state in which the Q output of the last D latch of the address generator is selected. 3. The first D latch of the read address generator has a set input, and the D latch of each number from the second to the last of the read address generator and the first of the write address generator. The D-latch of each number from the second to the last has a reset input, and sets the first D-latch of the read address generating section at the same time at the same time as each of the second to last number of the read address generating section. 3. The semiconductor delay device according to claim 1, wherein the numbered D latches and the numbered D latches of the first to last numbers of the write address generator are reset.