JPH0628151A - Parallel latch circuit for serial data - Google Patents

Abstract

PURPOSE:To decrease the circuit scale by using a shift register which shift a maximum number of bits of data and a latch circuit which performs parallel latching operation in common. CONSTITUTION:A 1st shift register 1a which shifts and holds the data of the head block in input data while an enable signal is applied, a 2nd shift register 1b which shifts and holds the data of the 2nd block while the enable signal is applied, and a 3rd shift register 1c which shifts and holds the data of the 3rd block while the enable signal is applied are provided in parallel. Further, this circuit is provided with an enable signal generation part 2 which outputs the enable signal to the 1st shift register 1a, 2nd shift register 1b, and 3rd shift register 1c in order and the serial/parallel conversion of the data is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel latch circuit for serial data.

[0002]

2. Description of the Related Art FIG. 3 is a diagram showing a configuration of a conventional example circuit, and FIG. 4 is a diagram showing a timing of the conventional example circuit.

In FIG. 3, 11 is an N-bit shift register, and 12 is a timing generator. 13a is a first latch circuit, 13b is a second latch circuit, and 13c is a third latch circuit.

In FIG. 4, (a) is a clock. Note that (b) to (d) are signals output from the timing generation unit 12, (b) is an L-bit latch signal output at the timing of the L-th clock (a), and (c) is (L + M). The M-bit latch signal output at the timing of the th clock (a), and (d) is the N-bit latch signal output at the timing of the (L + M + N) th clock (a). And
(e) is input data following the serial.

Further, (f) and (g) are the first latch circuit 13a.
(F) is the first 1-bit latch data in the L data of the first block in the input data (e), and (g) is the data output from the L data of the first block. This is the final L-bit latch data.

(H) and (i) are the data output from the second latch circuit 13b, and (h) is the first 1-bit latch of the M data of the second block in the input data (e). Data, (i) is the final M-bit latch data among the M data of the second block.

Further, (j) and (k) are the data output from the third latch circuit 13c, and (j) is the first 1 of the N data of the third block in the input data (e). Bit latch data, (k) is the final N bit latch data among the N data of the third block.

As shown in FIGS. 3 and 4, 1, 2, 3, ...
..Serial input data (e) consisting of a first block following L, a second block following M, a third block continuing 1, ... N, and an N-bit shift register in order from the first bit If added to 11, N-bit shift register 11
If the maximum capacity width of N is N bits, data is output from the N-bit shift register 11 with an N-bit capacity width.

When the data having the maximum N-bit capacity width is latched every arbitrary bit from the first bit and serial / parallel conversion is performed, as shown in FIG.
If the maximum bit width of L, M, N is N bits,
An N-bit shift register 11 of N-bit capacity, a first latch circuit 13a of L-bit capacity, a second latch circuit 13b of M-bit capacity, and a third latch circuit 13c of N-bit capacity.
It is a circuit composed of three latch circuits.

In this case, the first latch circuit 13a latches L data of 1 to L in the leading block of the input data (e) with the L bit latch signal (b), and the first latch circuit 13a outputs 1 Th 1-bit latch data (f) ~ L
The th L-bit latch data (g) is output.

In the second latch circuit 13b, the input data (e)
1 to M data in the second block in
Latch with the bit latch signal (c), and the second latch circuit 13b
(L + 1) th 1-bit latch data (h) to (L
The + M) th M-bit latch data (i) is output.

Then, in the third latch circuit 13c, N pieces of data 1 to N in the third block in the input data (e) are latched by the N-bit latch signal (d), and the third latch circuit 13c outputs the data. (L + M + 1) th 1-bit latch data (j) to (L + M + N) th N-bit latch data
Output (k).

In this method, the total number of bits (L + M + N)
And the maximum bit width N increases, the maximum bit width N
Becomes larger, the first latch circuit 13a and the second latch circuit 13a
The number of gates of each latch circuit of 13b and the third latch circuit 13c and the register of the N-bit shift register 11 increases.

[0014]

Therefore, in the conventional parallel latch circuit for serial data, there is a problem that the number of gates of the latch circuit and the shift register increases.

An object of the present invention is to reduce the circuit scale by sharing a shift register for shifting the maximum number of bits of data and a latch circuit for parallel latching.

[0016]

In order to achieve the above object, as shown in FIG. 1, while the enable signal is applied, the data of the first block in the input data is shifted, and when the enable signal ends, the shift is performed. A first shift register 1a that holds the result until the end of the input data, and a data of the second block next to the first block in the input data is shifted while the enable signal is applied, and when the enable signal ends, the shift is performed. A second shift register 1b that holds the result until the end of the input data, and shifts the data of the third block next to the second block in the input data while the enable signal is applied, and shifts when the enable signal ends. Third shift registers 1c for holding the results until the end of the input data are provided in parallel, and the first shift register 1a is further provided. Second shift register 1b and the third
The shift register 1c is provided with an enable generation unit 2 that sequentially outputs an enable signal, and is configured to perform serial / parallel conversion of data.

[0017]

According to the present invention, as shown in FIG. 1, a first shift register 1a, a second shift register 1b, and a third shift register 1c are provided in parallel. In the first shift register 1a, input data is applied while an enable signal is applied. The data of the first block in the block is shifted, and when the enable signal ends, the shift result is held until the input data ends.

In the second shift register 1b, the data of the second block next to the input data is shifted while the enable signal is applied, and when the enable signal ends, the shift result is held until the input data ends. To do so.

In the third shift register 1c, the data of the third block in the input data is shifted while the enable signal is applied, and when the enable signal ends, the shift result is held until the input data ends. To do so.

Therefore, from the enable generation unit 2, the first
By sequentially outputting the enable signals to the shift register 1a, the second shift register 1b, and the third shift register 1c, it becomes possible to configure a circuit that performs serial / parallel conversion of data.

[0021]

Embodiments of the present invention will be described in detail below with reference to FIGS. FIG. 1 is a diagram showing a configuration of an embodiment circuit of the present invention, and FIG. 2 is a diagram showing a timing of the embodiment circuit of the present invention.

In FIG. 1, 1a is a first shift register,
1b is a second shift register, and 1c is a third shift register. 2 is an enable generation unit. Figure 2
In, (a) is a clock. Note that (b) is the input data that follows the serial.

Note that (c) to (e) are signals output from the enable generator 2, and (c) is an L that outputs'H 'at the timing of the width of the first to Lth clocks (a). Bit enable signal, (d) is M which outputs'H 'at the timing of the width of (L + 1) th to (L + M) th clock (a)
Bit enable signal, (d) is (L + M + 1) th ~
This is an N-bit enable signal that outputs'H 'at the timing of the width of the (L + M + N) th clock (a).

Further, (f) and (g) are the first shift register
It is the data that outputs'H 'from 1a, (f) is the first 1-bit latch data in the L data of the first block in the input data (b), and (g) is the L of the first block.
It is the final L-bit latch data of the data.

(H) and (i) are the data output from the second shift register 1b, and (h) is the first 1-bit latch data in the M data of the second block in the input data (b). , (I) are the final M-bit latch data in the M data of the second block.

Further, (j) and (k) are the third shift register 1c.
(J) is the first 1-bit latch data among the N data of the third block in the input data (b), and (k) is the N data of the third block. Is the final N-bit latched data.

As shown in FIGS. 1 and 2, the first shift register 1a having an arbitrary L bit length, the second shift register 1b having an arbitrary M bit length, and the third shift register 1c having an arbitrary N bit length, respectively. In parallel with 1, 2, 3, ...
Serial input data (b) consisting of a first block followed by L, 1 ... M followed by a second block 1, ... N followed by a third block is added.

Next, each enable terminal (E) for controlling the operation of the first shift register 1a, the second shift register 1b, and the third shift register 1c by the enable generator 2
When the data to be latched to the N terminal) has completely entered the target shift register, the enable signal input to the EN terminal is changed from'H 'to'L' to disable the first shift register 1a, 2 shift register 1b,
The operation of each shift register is stopped in the order of the third shift register 1c.

Then, after that, the first shift register 1a, the second shift register 1b, and the third shift register 1b.
1c is used as a latch circuit. This operation is L, M,
By performing each arbitrary bit length of N bits,
All the first shift register 1a and the second shift register 1
b, where the operation of the third shift register 1c has stopped,
The data is retained as it is.

After the processing of the held data is completed, the EN signal from the enable generator 2 is set to "H" to activate the first shift register 1a, the second shift register 1b and the third shift register 1c. 1'2 '... and subsequent input data (b) are repeatedly shifted and held.

By operating in this manner, each bit data of L bit width, M bit width and N bit width is latched in sequence.

[0032]

As is apparent from the above description, according to the present invention, in a circuit for sequentially latching serial data for each arbitrary bit from the first bit, "the next serial input until the processing of the latched data is completed. Under the condition that "data is not accepted", there is an effect that the scale of the circuit can be reduced by eliminating the need for a shift register that shifts input data.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment circuit of the present invention.

FIG. 2 is a diagram showing a timing of a circuit according to an embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a conventional example circuit.

FIG. 4 is a diagram showing a timing of a conventional example circuit.

[Explanation of symbols]

 1a is the first shift register 1b is the second shift register 1c is the third shift register 2 is the enable generator

Claims (1)

[Claims] 1. A first shift register (1a) which shifts data of a leading block in input data while an enable signal is applied, and holds the shift result until the input data ends when the enable signal ends. A second shift register (1b) that shifts the data of the second block next to the first block in the input data while the enable signal is applied, and holds the shift result until the input data ends when the enable signal ends. While the enable signal is being applied, the data in the third block next to the second block in the input data is shifted, and when the enable signal ends, the third shift register that holds the shift result until the input data ends ( 1c) are respectively provided in parallel, and further paired with the first shift register (1a), the second shift register (1b) and the third shift register (1c). A parallel latch circuit for serial data, comprising: an enable generation unit (2) for sequentially outputting an enable signal for performing serial / parallel conversion of data.