JPH0555831A - Optional waveform generator - Google Patents

Abstract

PURPOSE:To remove the limitation of the number of waveform data by simultaneously reading out each plural data from waveform data stored in two waveform memories in accordance with addresses alternately added to the memories and loading the read data to a shift register to speed up data reading. CONSTITUTION:The waveform memories 11, 12 are respectively constituted so as to simultaneously output waveform data corresponding to N addresses. An address generating part 13 generates an optional 1st address and the 2nd address preceding N addresses from the 1st address and adds its outputs to an address selector 14. The selector 14 alternately distributes the two addresses to the memories 11, 12, which output 2N waveform data in accordance with the applied addresses and add them to a data selector 15. The selector 15 is driven synchronously with the switching of the selector 14, alternately distributes the input data to outputs to the shift register 16. The register 16 shifts the 2N waveform data. Consequently limitation or the formation of waveform data can be removed.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to an arbitrary waveform generator,
More specifically, it relates to relaxation of restrictions on the number of waveform data.

[0002]

2. Description of the Related Art Generally, an arbitrary waveform generator is configured to sequentially read waveform data stored in a waveform memory to a DA converter and obtain an analog signal waveform output.

However, the cycle time of the waveform memory for storing the waveform data cannot keep up with the required speed. Therefore, for example, as shown in FIG. 4, a plurality (N, for example, 8) of waveform data are read from the waveform memory 1 at a time, loaded into a high-speed shift register 2 and converted into a required speed, and DA is converted. Outputting to the converter 3 is being performed. The read cycle in this case is N times the shift clock cycle of the shift register 2 (8 in the case of FIG. 4).
Double).

[0004]

However, in such a configuration, since N (eight in the case of FIG. 4) waveform data is one unit, the number of waveform data written in the waveform memory 1 is N. However, there is a problem that the degree of freedom in creating waveform data is reduced.

The present invention has been made in view of the above problems, and an object thereof is to provide an arbitrary waveform generator which eliminates the limitation of the number of waveform data.

[0006]

An arbitrary waveform generator according to the present invention converts parallel waveform data output from a waveform memory into serial waveform data by a data speed-up circuit, and outputs D
In the arbitrary waveform generator configured to be added to the A converter, the data speed-up circuit is provided with an address N
Two waveform memories configured to be able to simultaneously output the waveform data for the number of pieces, and an address generator for outputting an arbitrary first address and a second address which precedes the first address by N pieces. Section, an address selector for alternately distributing two addresses output from the address generating section to the two waveform memories, and a data selector for alternately distributing and outputting the output data of the two waveform memories And a shift register for shifting the 2N pieces of waveform data output from the data selector, and a clock controller for controlling the operation timing of each unit.

[0007]

The waveform data stored in the two waveform memories are simultaneously read out N times in accordance with the addresses alternately applied through the address selectors, and are further loaded alternately into the shift register through the data selectors to speed up the operation. It

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of the principle of the present invention.
In FIG. 1, reference numerals 11 and 12 denote two waveform memories composed of memory banks 0 and 1, each of which is capable of simultaneously outputting waveform data for N addresses. Thirteen
Is an address generator, which outputs an arbitrary first address and a second address N-numbered ahead of the first address. Reference numeral 14 is an address selector which alternately distributes the two addresses output from the address generator 13 to the two waveform memories 11 and 12. Reference numeral 15 is a data selector, which is switched and driven in synchronization with the switching of the address selector 14, and the two waveform memories 1
The output data of 1 and 12 are alternately distributed and output. 1
A shift register 6 shifts the 2N pieces of waveform data output from the data selector 15. Reference numeral 17 denotes a clock controller that outputs a clock that controls the operation timing of each unit.

FIG. 2 is a block diagram of a specific example when N = 8. Address adrs0 applied to the A terminal and address adr applied to the B terminal of the address selector 14.
Since s1 is N = 8, assuming that the waveform data stored in the waveform memories 11 and 12 is in word units,
There is a relationship of adrs1 = adrs0 + 10 _H. The address selector 14 outputs the address adrs0 applied to the A terminal to the YA terminal and outputs the address adr applied to the B terminal in accordance with the select signal applied to the SEL terminal.
Either s1 is output to the YB terminal, or the address adrs0 applied to the A terminal is output to the YB terminal and the address adrs1 applied to the B terminal is output to the YA terminal.

The address output from the YA terminal of the address selector 14 is applied to the waveform memory 11 via the latch 18, and the address output from the YB terminal is latch 19.
Is added to the waveform memory 12 via the.

Each of the waveform memories 11 and 12 includes a latch 1
According to the addresses added from 8 and 19, a total of 16 pieces of waveform data are output at a time, 8 pieces in total. Waveform memory 11
The output data of 1 is applied to the A terminal of the data selector 15 via the latch 20, and the output data of the waveform memory 12 is applied to the B terminal of the data selector 15 via the latch 21.

The data selector 15 outputs the output data of the waveform memory 11 applied to the A terminal to the YA terminal and the output data of the waveform memory 12 applied to the B terminal to the YB terminal according to the select signal applied to the SEL terminal. Either output is performed or output data of the waveform memory 11 applied to the A terminal is output to the YB terminal and output data of the waveform memory 12 applied to the B terminal is output to the YA terminal.

The shift register 16 has a data selector 1
The waveform data selected in 5 is loaded. The address terminals of the waveform memories 11 and 12 are connected to the CPU address bus via the buffer 22, and the data terminals are connected to the CPU data bus via the buffer 23. These are for setting and storing the waveform data in the waveform memories 11 and 12. The waveform data is alternately written in the order of 11 → 12 → 11 → 12 → ... Is essentially irrelevant.

The operation of FIG. 2 will be described with reference to the timing chart of FIG. 3 in the case where a waveform is composed of 19 pieces of waveform data. In this case, from the relationship of 19 = 8 + 8 + 3, three pieces of waveform data become fractional data.

(A) is a basic high-speed clock input to the clock controller 17. (B) is a clock obtained by dividing the high-speed clock by ⅛, and is supplied from the clock controller 17 to each unit. (C) is a load pulse LOD ′ supplied from the clock controller 17 to the shift register 16. The dash represents a negative logic operation. (D) is shift register 1
6 is the waveform data to be loaded. (E) is a selection signal SEL supplied from the clock controller 17 to the address selector 14 and the data selector 15.
(F) is waveform data output from the waveform memories 11 and 12. (G) is waveform data latched by the latches 20 and 21. (H) is high-speed data output from the shift register 16. (I) is the waveform memory 11,
This is the address given to the T.

First, a leading address in which 19 pieces of waveform data are stored is given as adrs0 shown in (i), and an address advanced by 10 _H from adrs0 is given to adrs1. At this time, the address selector 1
4 is added from the clock controller 17 (e)
It is assumed that it is set to select A → YA and B → YB by the selection signal SEL shown in FIG.

The waveform memory 11 is provided with adrs0, and the waveform memory 12 is provided with adrs1. As a result, the waveform data shown in FIG.
Simultaneously outputs eight pieces of waveform data starting from adrs0, and the waveform memory 12 simultaneously outputs eight pieces of waveform data starting from adrs1.

16 output from the waveform memories 11 and 12
The waveform data for each of the waveforms is, as shown in FIG.
After being latched at 1, it goes through the data selector 15 controlled and driven by the clock controller 17 so as to be synchronized with the address selector 14, and then the load pulse LO shown in (c).
It is loaded into the shift register 16 according to D '. Then, of the loaded 16 waveform data shown in (d), the first eight data 0-7 are speeded up as shown in (h). These eight are the first eight of 19 = 8 + 8 + 3.

Next, as the address of the waveform memory shown in (i), adrs1 is set in adrs0, and adrs1 is set.
adrs1 + 10 _H is set in s1. In other words, the address has advanced by 10 _H. At this time, the address selector 14 receives A-> YB, B-> by the selection signal SEL (e) output from the clock controller 17.
YA is set to be selected, and the waveform memory 11 stores a
drs1 is provided, and the waveform memory 12 is provided with adrs0.

As a result, the shift register 16 has
According to the load pulse LOD ′ shown in (c), the waveform data output from the waveform memories 11 and 12 are loaded in this order in the waveform memories 12 and 11. At this stage, the waveform memory 12 outputs the middle eight waveform data of 19 = 8 + 8 + 3, and the waveform memory 11 outputs the last 3 of 19 = 8 + 8 + 3.
Outputs individual waveform data.

Here, the clock controller 17 knows that the latter eight of the waveform data loaded into the shift register 16 include a fraction, and the high speed clock is 8 + 3 as shown in (a). Control is performed to output 11 pieces. Of the 16 loaded waveform data shown in (d), the middle 8 to 0 and the last 3 8
10 to 10 are accelerated as shown in (h).

Thus, by using as the waveform memories 11 and 12 those capable of operating at a cycle of the high-speed clock divided by 8 shown in (b), it is possible to obtain an arbitrary number of data without being restricted by a multiple of 8. Waveform data can be output.

[0023]

According to the present invention described in detail above, there is no limitation when creating waveform data as in the prior art, and even if a low-speed waveform memory is used, there is a high degree of freedom in waveform data generation. The arbitrary waveform generator can be realized.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram of the specific example of FIG. 1 when N = 8.

FIG. 3 is a timing chart illustrating the operation of FIG.

FIG. 4 is a block diagram of a conventional device.

[Explanation of symbols]

 11, 12 Waveform memory (memory bank) 13 Address generator 14 Address selector 15 Data selector 16 Shift register 17 Clock controller

Claims (1)

[Claims] 1. An arbitrary waveform generator configured to convert parallel waveform data output from a waveform memory into serial waveform data by a data speedup circuit and add the serial waveform data to a DA converter, wherein the data speedup circuit comprises: Two waveform memories each configured to simultaneously output waveform data for N addresses, an arbitrary first address, and a second address N times ahead of the first address. An address generator for outputting, an address selector for alternately distributing the two addresses output from the address generator to the two waveform memories, and alternately distributing output data of the two waveform memories An output data selector, a shift register for shifting 2N waveform data output from the data selector, and an operation timing of each part Arbitrary waveform generator, characterized in that it is constituted by a clock controller, capital controlled.