JP3103746B2 - Semiconductor delay device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor delay device used for signal processing.

[0002]

2. Description of the Related Art A conventional semiconductor delay device will be described below. FIG. 3 shows a circuit diagram of a conventional semiconductor delay device.
In FIG. 3, reference numeral 32 denotes a memory cell unit. 31 is a read address generation unit. 33 is a write address generator. The read address generation unit 31 and the write address generation unit 33 are each configured by a D latch, and each of the D latches 31 ₁ , 33 ₁ , 31 ₂ , 33 ₂ ,.
1 _n , 33 _n are connected in order to each D input, and the Q output of the last D latch 33 _n is connected to the D output of the first D latch 31 ₁ .
Connected to the input and so on. A set with D latches only the D latch 33 _n, otherwise is composed of a D-latch with Reset. The memory cell section 32 includes n (n is an integer) memory cells 32 ₁ , 32 _{2 ,.}
Are arranged in a line. 34 is a reset input terminal for inputting a reset signal, 35 is a clock input terminal for receiving a common clock signal, 36 is a time-series signal input terminal,
37 is a time-series signal output terminal.

The operation of the semiconductor delay device thus configured will be described below. First, when a reset signal is input from the reset input terminal 34, the D latch 3
3 _n only the output Q is set to "H", the other D latches _{31 1, 33 1, 31 2} , 33 2 ~31 n is set to "L" by the reset operation. In this state, when the first clock signal is input from the clock input terminal 35, D
The output Q of the latch 31 ₁ becomes “H” and the D latch 33 _n
Output Q is in the "L" state. At this time, the D latch 31
_{By 1} output Q becomes "H" 1 th memory cell 32 ₁ performs a read operation, and outputs to the sequence signal output terminal 37 when the signal of the memory cell 32 ₁ from the data output terminal O.

[0004] Next, when the clock input terminal 35 is two of the clock signal is input, D latch 33 ₁ of the output Q becomes "H", D output Q of the latch 31 ₁ becomes "L". Memory cell 32 ₁ performs a write operation by D output Q of the latch 33 ₁ becomes "H", the time-series signal input terminal 36 one clock memory series input signal from the data input terminal I when input from write to the cell 32 _1.

Similarly, every time a clock signal is input from the clock input terminal 35, the state of "H" shifts from the D latch 31 ₂ → 33 ₂ →... → 31 _n → 33 _n . The memory cells 32 ₂ , 32 _{3 to} 32 _n−1 , 32 _n perform read / write operations, and when a clock signal is further input, the D latch 31 ₁ is again set to “H”, and the memory cell 32 ₁ Is performed, and the same operation is repeated thereafter.

Thus, the memory cells 31 ₁ , 32 ₂ ,
By repeatedly performing the read / write operations of 32 _{3 to} 32 _n−1 and 32 _{n in} a loop, the signal input in time series to the time-series signal input terminal 36 becomes a signal delayed by 2n clock periods. It is output from the series signal output terminal 37.

[0007]

However, in the above-mentioned conventional configuration, only a normal rotation delay operation (so-called first-in first-out operation) for delaying a time-series input signal and outputting the signal in the same order as the input order can be performed. It has not been possible to perform an inversion delay operation (so-called first-in, last-out operation) for delaying a sequence input signal and outputting the signal in an order reverse to the input order.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and to provide a semiconductor delay circuit having both functions of a normal rotation operation and an inversion delay operation.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor delay device comprising a plurality of memory cells arranged in a line from a first number to a last number and having a data input terminal and a data output terminal commonly connected. And a first clock to a final clock corresponding to each memory cell of the memory cell section, and a common clock is input and a Q output is supplied to each memory cell of the memory cell section as a read signal. A read address generating section comprising a plurality of D latches, and a D clock which is arranged in a line from the first to the last corresponding to each memory cell of the memory cell section, receives a common clock as input, and receives each D latch of the read address generating section. Q of
A write address generator comprising a plurality of D latches, each of which outputs a D input and supplies a Q output to each memory cell of the memory cell section as a write signal, and a memory address corresponding to each memory cell of the memory cell section. First
A selector unit comprising a plurality of selectors arranged in a line from the number to the last number and selecting a supply source of D input to each D latch of the read address generation unit from Q outputs of the plurality of D latches of the write address generation unit; A selection control unit for selecting a supply destination of the Q output of the last D latch of the write address generation unit from the D inputs of the plurality of D latches of the read address generation unit, wherein the selection control unit is configured to store the memory cell in the first mode. The supply destination of the Q output of the last D latch of the write address generation unit is changed so that the read / write operation of each memory cell of each unit is repeated only in the first to last directions. In the second mode, the read / write operation of each memory cell in the memory cell section is selected from the D input of the latch, and the read / write operation is performed in the first to last direction and the last to last operation. D of a plurality of D latches supply destination read address generator of the Q output of the last number of the D-latch of the write address generator so as to repeat alternately the direction of the turn
Each of the read address generators selects from the input, and the respective selectors of the selector unit operate such that the read / write operation of each memory cell of the memory cell unit is repeated only in the first to last directions in the first mode. The source of the D input to the D latch is selected from the Q outputs of the plurality of D latches of the write address generator, and the read / write operation of each memory cell in the memory cell section is performed from the first to the last in the second mode. And the source of the D input to each of the D latches of the read address generation unit is alternately repeated in the direction from the last address to the first to the first direction.
The selection is made from the Q output of the latch.

According to a second aspect of the present invention, there is provided a semiconductor delay device comprising a plurality of memory cells arranged in a line from a first number to a last number and having a data input terminal and a data output terminal commonly connected to each other; And a plurality of D latches which are arranged in a line from the first to the last in correspondence with each of the memory cells and receive a common clock and supply a Q output to each memory cell of the memory cell section as a read signal. The read address generator and the first to last memory cells are arranged in a row corresponding to each memory cell of the memory cell section, and a common clock is input.
A plurality of Ds, each of which supplies an input and a Q output to each memory cell of the memory cell section as a write signal, respectively.
A write address generator comprising a latch, and a source of D input to each D latch of the read address generator which are arranged in a line from the first to the last corresponding to each memory cell of the memory cell section. A selector section including a plurality of selectors for selecting from Q outputs of a plurality of D latches of an address generation section;
A selection control unit for selecting a supply destination of the Q output of the latch from the D inputs of the plurality of D latches of the read address generation unit, wherein the selection control unit supplies the Q output of the last D latch of the write address generation unit First, in the first mode, the read address generation unit is connected via the first selector of the selector unit so that the read / write operation of each memory cell of the memory cell unit is repeated only in the first to last directions. Select the D input of the first D latch, and read / read each memory cell of the memory cell section in the second mode.
The first address of the read address generation unit via the first selector of the selector unit is such that the write operation is alternately repeated in the first to last direction and the last to first direction.
The state where the D input of the D-th latch is selected and the state where the D input of the last D-latch of the read address generation section is selected via the last selector of the selector section are switched. The selector selects the first D-latch of the read address generator as a source of the D input to the first D-latch.
In the mode, the Q output of the last D-latch of the write address generator is controlled via the selection controller so that the read / write operation of each memory cell of the memory cell section is repeated only in the first to last directions. In the second mode, the write address generator is configured to alternately repeat the read / write operation of each memory cell in the memory cell section in the first to last direction and the last to first direction. The state of selecting the Q output of the first D-latch and the state of selecting the Q output of the second D-latch of the write address generator are switched between the second and the last one of the selector. The selectors of the numbers up to the number of the read address generator are the sources of the D input to the D latches of the numbers from the second to the last number before the last number of the read address generation unit. Reading of each memory cell of the parts,
In order to repeat the write operation only in the direction from the first to the last, the Q outputs of the D latches of the respective numbers from the first to the last two before the write of the write address generator are selected, and In the 2nd mode, the first address of the write address generator is set so that the read / write operation of each memory cell of the memory cell section is alternately repeated in the first to last direction and the last to first direction. To select the Q outputs of the D latches of the respective numbers from the first to the last two numbers, and select the Q outputs of the D latches of the respective numbers from the third to the last number of the write address generator. Switch the state and the last selector of the selector section,
As a supply source of the D input to the last D latch of the read address generator, in the first mode, the read / write operation of each memory cell of the memory cell section is repeated only in the direction from the first to the last. In the second mode, the Q output of the D latch of the number immediately before the last number of the write address generator is selected, and the read / write operation of each memory cell in the memory cell section is performed in the first to last directions. And the state of selecting the Q output of the D-latch of the number immediately before the last number of the write address generation unit, and the generation of the write address The state where the Q output of the last D latch of the section is selected is switched.

According to a third aspect of the present invention, in the semiconductor delay device of the first or second aspect, the first D latch of the read address generator has a set input, and the first address of the read address generator has a set input. Each of the second to last D-latches and the first to last D-latch of the write address generator has a reset input, and the first address of the read address generator at start-up. At the same time as setting the D latch,
The D-latch of each number from the first to the last number and the D-latch of each number from the first to the last number of the write address generator are reset.

[0012]

According to the configuration of the present invention, the read / write operation of each memory cell of the memory cell section is performed in the first mode by the selection operation of the selector section and the selection control section.
A forward rotation delay that repeats only in the direction from the turn to the last turn is performed,
In the second mode, an inversion delay that alternately repeats the read / write operation of each memory cell in the memory cell section in the first to last direction and the last to first direction is performed.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor delay device according to the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a semiconductor delay device according to an embodiment of the present invention.
In FIG. 1, a memory cell section 2 includes a plurality of memory cells 2 ₁ , 2 arranged in a line from a first number to a last number (n number).
₂ ,..., 2 _n−1 , 2 _n , the data input terminal I and the data output terminal O are commonly connected, the data input terminal I is connected to the time-series signal input terminal 10, and the data output terminal O is It is connected to the series signal output terminal 11.
In this case, the memory cell _{2 1, 2 2 ~2 n-} 1, 2 n , when the read control signal "H" to the read control signal input terminal R is inputted, reads out the data to the data output terminal O When a write control signal of “H” is input to the write control signal input terminal W, data is written from the data input terminal I.

The read address generator 1 includes a memory cell
Each memory cell 2 of the section 2₁, 2_Two, ..., 2_n-1, 2_n
Are arranged in a line from the first to the last (n)
Multiple D latches 1₁, 1_Two, ..., 1_n-1, 1_nFrom
Become. This plurality of D latches 1 ₁, 1_Two, ..., 1_n-1, 1
_nIs a common clock input from the clock input terminal 6.
Input and input Q output to each memory of the memory cell unit 2.
Cell 2₁, 2_Two, ..., 2_n-1, 2_nRead control signal
Supplied to the input terminal R as a read control signal.
You.

[0015] In this case, D latch 1 ₁ is attached a set (S), D latch _{1 2, ..., 1 n-} 1, 1 n is with Reset (R), which are common to the reset input terminal 12 are connected to, the input of the reset signal of "H" to the reset input terminal 12, D latch 1 ₁ is set Q output becomes "H", D latch 1 _2, ..., 1 _n-1,
1 _n is reset and the Q output becomes “L”.

The write address generating unit 3 includes a memory cell
Each memory cell 2 of the section 2₁, 2_Two, ..., 2_n-1, 2_n
Are arranged in a line from the first to the last (n)
Multiple D latches 3₁, 3_Two, ..., 3_n-1, 3_nFrom
Become. This plurality of D latches 3 ₁, 3_Two, ..., 3_n-1, 3
_nIs a common clock input from the clock input terminal 6.
Input to the D address of the read address generator 1
Switch 1₁, 1_Two, ..., 1_n-1, 1_nQ output of each
D input and Q output of each memory cell unit 2
Memory cell 2₁, 2_Two, ..., 2_n-1, 2_nWriting
Write to the control signal input terminal W as a control signal
Supply. That is, the D latch 3₁ , 3_Two, ..., 3_n-1 ,
3_nD input of the read address generation unit 1
D latch 1₁ , 1_Two ~ 1_n-1 , 1_nConnected to the Q output of
ing. Also, the first D latch 3₁ Q output is
Kuta 4₁Input of B and selector 4_TwoConnected to the A input of
Have been. Last (nth) D latch 3_nThe Q output of
Selector 4_n-1B input and D input of selection control unit 5
It is connected. 2nd D latch 3_Two To (n-
1) D latch 3_n-1 Of the (k +
1) selector {k is 2,..., (N-1)} selector 4_Two,
…, 4_n-1Input A and the (k-1) th selector 4₁,
…, 4_n-2B input.

In this case, the D latches 3 ₁ , 3 ₂ ,.
_n-1 and _3n are all with reset. These are commonly connected to the reset input terminal 12, and when the "H" reset signal is input to the reset input terminal 12, the D latches 3 ₁ and 3 _{2 are provided.} , ..., 3 _n-1 , 3 _n are reset and Q
The output becomes "L". The selector unit 4 includes the memory cell unit 2
Each of the memory cell 2 _1, 2 _2, ..., 2 _n-1, 2 _n final number from the first number corresponds to the (n-th) a plurality of selector 4 arranged in a row up to _1, 4 _2, ... , 4 _n . The plurality of selectors _{4 1, 4 2, ...,} 4 n is the read address generation unit and each of the D latches ₁ 1 1, 1 _2, ..., 1 _n-1,
The source of the D input to 1 _n is selected from any two or three Q outputs of the plurality of D latches 3 ₁ , 3 ₂ ,..., 3 _n-1 , 3 _n of the write address generator 3. That is, the outputs Q of the selectors 4 ₁ , 4 ₂ to 4 _n−1 , 4 _n are output from the D latches 11 ₁ , 1 ₂ to 1 of the read address generator 1, respectively.
_n-1 and 1 _n are connected to D inputs.

[0018] In this case, each selector 4 _first selector portion 4, 4 _2, ..., 4 _n is in the first mode, a plurality of memory cells 2 _{1, 2} 2, ..., read-out of 2 _n-1, 2 _n - a write operation from the first number of each of the read address generating unit 1 to repeat in the direction of the final numbers only D latch 1 _{1,
1 2, ..., 1 n-} 1, 1 a plurality of D-latch 3 ₁ of the address generating unit 3 writes the source of the D input of the _n, 3 _2, ..., 3
_n-1, 3 _n either two to choose from three Q outputs. In the second mode, the read / write operation of the plurality of memory cells 2 ₁ , 2 ₂ ,..., 2 _n−1 , 2 _n is performed in the first to last direction and the last to first direction. The source of the D input to each of the D latches 1 ₁ , 1 ₂ ,..., 1 _n−1 , 1 _n of the read address generation unit 1 is alternately repeated. _1, 3 _2, ..., is selected from 3 _n-1, 3 _n or two to three of Q output.

More specifically, the first section of the selector section 4 will be described.
Number selector 4₁Is the input of the selection signal for
S supplied from force terminals 7 and 8₁Input, S_TwoSelection for input
Input, A input, B input and Q output
And C input, select S₁Input is "L", S_Two
When the input is "L", the C input is selected and S₁Input is
“L”, S_TwoWhen the input is "H", select the B input,
S₁When the input is "H", S_TwoRegardless of input
First, an operation of selecting the A input is performed. And select signal input
S to be supplied to terminals 7 and 8₁Input, S_TwoInput selection signal
Set appropriately in the first mode and the second mode respectively
As a result, the first D
Switch 1₁As the source of the D input to the
Of the write address generator 3 via the selection controller 5
Last D latch 3_nQ output is selected. Also, the second
In the mode, the first D of the write address generator 3
Latch 3₁To select the Q output of and the write address
Second D-latch 3 of generator 3 _TwoTo select the Q output of
Switch between states.

Further, the selectors 4 ₂ ,..., 4 _n−1 of the respective numbers from the second number to the number immediately before the last number of the selector section 4
Operates to select the A input when the selection signal to the S input supplied from the selection signal input terminal 7 is "H" and to select the B input when the selection signal is "L". Then, the selection signal to the S input supplied to the selection signal input terminal 7 is appropriately set in the first mode and the second mode, respectively, so that the read address generation unit 1 from the second to the last one before the last number D-latch 1 ₂ of each number from numbers, ..., as the supply source of the D input to 1 _n-1, the first mode, the first number of the write address generator 3 to the two previous number of the last number D-latch 3 ₁ of each number, ..., selects 3 _n-2 of the Q output, respectively. Also,
The second mode, the write address generator D latch 3 ₁ of each number from No. 1 up to two previous number of the last number of 3, ..., state and write address 3 _n-2 of the Q outputs respectively selected .., 3 _n of the generator 3 are switched from a state of selecting the Q output of each of the D latches 3 ₃ ,.

Further, the last selector 4 _n of the selector section 4 has an A input when the selection signal to the S input supplied from the selection signal input terminal 9 for switching between normal and inversion is “H”,
At the time of "L", the operation of selecting the B input is performed. Then, the selection signal to the S input supplied to the selection signal input terminal 9 is changed to the first signal.
By appropriately setting the mode and the second mode, the source of the D input to the last D latch 1 _n of the read address generator 1 can be set as the last source of the write address generator 3 in the first mode. The Q output of the preceding D latch 3 _n-1 is selected. Further, in the second mode, the state in which the Q output of the D latch 3 _n−1 of the number immediately before the last number of the write address generation unit 3 is selected and the state in which the write address generation unit 3 and a state for selecting the Q output of the turn of the D-latch 3 _n.

The selection control unit 5 determines the supply destination of the Q output of the last (n-th) D latch 3 _n of the write address generation unit 3 and the two D latches 1 ₁ , 1 _{n of the} read address generation unit 1.
From the D input. That is, the selection control unit 5 connects the D input to the Q output of the D latch 3 _n , connects the Q ₁ output to the B input of the selector 4 _n , and connects the Q ₂ output to the A output of the selector 4 ₁ .
Connected to input.

In this case, the selection control unit 5 operates in the first mode.
Has a plurality of memory cells 2₁, 2_Two, ..., 2_n-1, 2_n
Read / write operation from the first to the last
Only the last number of the write address generator 3 is repeated.
D latch 3_nReads the output destination of the Q output and issues an address.
Two D latches 1 of raw part 1₁, 1_nSelect from D input of
You. In the second mode, a plurality of memory cells 2₁,
2_Two, ..., 2_n-1, 2 _nRead / write operation
In the direction from No. 1 to the last and from the last to No. 1
The last number of the write address generator 3 so as to repeat each other
D latch 3_nReads the output destination of the Q output and issues an address.
Two D latches 1 of raw part 1₁, 1_nSelect from D input of
You.

To be more specific, the selection control unit 5 sets the D
If the input is "L", Q ₁ output, Q ₂ output outputs the "L" regardless of the S input. In the case of the D input is "H", Q ₁ outputs "L" when the selection signal to the S input supplied from the selection signal input terminal 9 is "H", Q ₂ output becomes "H" ( Q ₂ selects the output), when the selection signal to the S input is "L" Q ₁ output is "H", Q ₂ outputs "L"
Become (Q ₁ selects the output) to an operation. Then, the selection signal to the S input supplied to the selection signal input terminal 9 is changed to the first signal.
In the first mode, the first selector 4 of the selector unit 4 is set as the destination of the Q output of the last D latch 3 _n of the write address generator 3 by appropriately setting the mode and the second mode. ₁ to select the D input of the _first D latch 11 of the read address generator 1. The second mode, the read address generator 1 through the selector 4 ₁ of the first number of selector 4 1
And a state of selecting the D latch 1 _n D input of the last number of the read address generator 1 through the turn of the D final number of the selector 4 _n latches 1 ₁ state and selector 4 for selecting a D input .

FIG. 2 is a timing chart of the semiconductor delay device of the embodiment shown in FIG. 2A is a timing chart at the time of the inversion operation, and FIG. 2B is a timing chart at the time of the normal operation. In FIG. 2, 22 is the Q output of the D latch 1 _n , 23 is the Q output of the D latch 3 _n ,
24 Q ₁ outputs of the selection controller 5, 25 Q ₂ output of the selection control section 5, the clock signal of the clock input terminal 6 26,
27 is a timing chart of the selection signal of the selection signal input terminal 7, 28 is a selection signal of the selection signal input terminal 8, and 29 is a timing chart of the selection signal of the selection signal input terminal 9.

The selection signal supplied to the selection signal input terminals 7 to 9 is generated by a timing generation circuit (not shown). The operation of the semiconductor delay circuit of this embodiment configured as described above will be described below. When a reset signal is input from the reset input terminal 12 at startup,
Read address generation unit 1 of the set with the D-latch 1 ₁ is set Q output becomes "H", the other D-latch 1 _2, ..., the state of "L" by all 1 _n-1, 1 _n is reset operation become. In this case, the memory cell 2 ₁ performs a read operation.

The first clock signal is applied to the clock input terminal 6.
Is input (20 in FIG. 2).₁ , 21₁ State), D
Latch 3₁ Becomes "H", and the memory cell 2₁ But
Perform a write operation. At this time, the selector 4₁Of B
Force, selector 4_TwoBecomes "H". Here,
Lecter 4₁The selection signal to₁Input is "L", S_TwoEntering
Since the power becomes "L", its Q output selects C input.
"L" is output. Selector 4_TwoQ output is A input
The force is output and the state becomes “H”. As a result,
When the lock signal is input from the clock input terminal 6
(20 in FIG. 2)_Two , 21 _Two State) D latch 1_Two Q output of
Only "H". At this time, the memory cell 2_TwoIs read
And perform the operation. Thus, the clock input terminal 6
D latch 1₁, ..., 1_n, 3
₁, ..., 3_n"H" state of the output of D latch 1₁ → D la
Switch 3₁ → D latch 1_Two → D latch 3_Two → ・ ・ ・ → D
Switch 1_{n- 1} → D latch 3_n-1 → D latch 1_n→ D latch
3_nTo memory cell 2₁ , 2_Two ~ 2_n-1 ,
2_nThe read / write operation is repeated in this order.
As a result, the time series input from the time series signal input terminal 10
The column signal is sequentially applied to the memory cell 2 ₁ , ..., 2_nWritten to
You. Up to this point, the same operation is performed for both the normal delay and the reverse
You. The following operation differs between the normal rotation delay and the inversion delay.

First, the case of the inversion delay will be described.
The clock signal continues to be input from the clock input terminal 6 and D
Latch 3_nBecomes "H" (see FIG. 2 (a)).
20 _Three State) Memory cell 2_nPerforms a write operation.
Selector 4_n-1B input and input of selection control unit 5
The force D becomes "H". At this time, the selection signal input terminal 9
The selection signal becomes "L". As a result, Q of the selection control unit 5
₁The output becomes "H". Selector 4_nQ output of
Selects the B input and outputs "H". Selector 4_n-1
"L" is output because "H" is input to the S input of
Is done. As a result, the next clock signal is input
And D latch 1_nBecomes "H" and the memory cell 2
_nIs performed. The next clock signal is
When pressed (20 in FIG. 2A)_Four State), D latch 3
_nBecomes "H" and the memory cell 2_nWrite action
Do the work. Selector 4_n-1B input and selection system
The input D of the control unit 5 becomes "H". At this time, select signal input
The selection signal of the terminal 9 becomes "H". As a result, selection control
Q of part 5_TwoAlthough the output becomes “H”, the selector 4₁Q out of
The force selects the C input and outputs "L". Also select
TA4_n-1Of the selector 4 changes to "L"._n-1
Outputs “H”. As a result, the next clock signal
Is input, the D latch 1_n-1 Becomes “H”
Memory cell 2_{n- 1} Is performed. Next
Is input, the D latch 3 _n-1 Output
Becomes “H” and the memory cell 2_n-1 Performs a write operation.
U. Thereafter, a clock signal is input from the clock input terminal 6.
Memory cell 2 every time_n-2→ ・ ・ ・ → 2_Two → 2₁ When
Reading and writing are sequentially performed. Memory cell 2₁ of
At the end of the write operation, the time-series signal input terminal 1
The first to n-th time-series signals input from 0 are
Time series signal delayed by 2n clocks from the nth to the 1st
The signal is output to the time-series signal output terminal 11 as a signal. Reversal late
Nobu is thus the memory cell 2₁ → 2_nIn the order (read
C) write, and then vice versa_n→ 2₁ Read in order
Read and write. Next is 2₁ → 2_nRead in the order
By performing read / write and repeating this operation,
Is realized. Next, the case of forward rotation delay is explained.
I will tell. A clock signal is input from the clock input terminal 6.
D latch 3_nIs "H" (see FIG. 2).
(B) 21_Three State) Memory cell 2_nIs a write operation
I do. Selector 4_n-1B input and block
5 becomes "H". At this time, select signal input terminal
The selection signal of the child 9 remains "H". As a result, the choice
Q of control unit 5_TwoThe output becomes "H". Selector 4₁Q of
The output selects the A input and outputs "H". Selector 4
_n-1Since "H" is input to the S input of "L",
Is output. As a result, the next clock signal is input.
(See 21 in FIG. 2B)_Three State), D latch 1₁ of
The output becomes “H” and the memory cell 2₁ Read operation
Done. When the next clock signal is input, the D
Chi 3₁ Becomes "H" and the memory cell 2₁ Is written
Performs only the operation. At this time, the selector 4₁B input and
Selector 4_TwoBecomes "H". Selector 4₁Is
S₁Input is “H”, S_TwoSince the input becomes “H”,
The Q output selects the A input and outputs “L”. Also,
Lecter 4_TwoOutput is A input, and is in “H” state
become. As a result, the next clock signal is input from terminal 6.
When pressed, D latch 1_Two Only the Q output of the
You. At this time, the memory cell 2_Two Performs a read operation. This
Then, a clock signal is input from the clock input terminal 6
Every time memory cell 2_Three→ ・ ・ ・ → 2_n-1 → 2 _nRead in order
Perform overwriting. Memory cell 2_nWrite operation
At the end of the process, input from the time-series signal input terminal 10.
The time series signals from No. 1 to No. n are
time series signal as a time series signal delayed by 2n clocks up to nth
Output to the column signal output terminal 11. This is the normal rotation delay
Sea memory cell 2₁ → 2_nWrite (read) in order
Mi, then 2₁ → 2_nRead and write in the order of
This is realized by repeating this operation.

[0029]

According to the semiconductor delay device of the present invention, a semiconductor delay device having both functions of a first-in first-out type normal rotation delay and a first-in last-out type inversion delay is provided by only adding a selector unit and a selection control unit. Can be realized with a minimum area increase.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor delay device according to an embodiment of the present invention.

FIG. 2 is a timing chart of a forward / reverse switching signal in one embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional semiconductor delay circuit.

[Explanation of symbols]

1, 31 read address signal generation unit 2, 32 memory cell unit 3, 33 write address signal generation unit 4 selector unit 5 selection control unit 6, 35 clock input terminal 7 selection signal input terminal 8 selection signal input terminal 9 selection signal input terminal 10,36 time series signal input terminals 11,37 chronologically signal output terminal 12, 34 reset input terminal 1 _1, 33 _n dated set D latch _{1 2 ~1 n, 3 1 ~3} n D latch 2 ₁ dated reset to 2 _n memory cells 4 ₁ to 4 _n selectors _{31 1 ~31 n, 33 1 ~33} n-1 with reset of the D-latch 32 ₁ to 32 _n memory cells 20 of the timing chart 21 during reverse operation during forward operation chart

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 7/00 H03K 5/135 G06F 5/06 WPI (DIALOG)

Claims (3)

(57) [Claims] 1. A memory cell section comprising a plurality of memory cells arranged in a line from a first number to a last number and having a data input terminal and a data output terminal commonly connected to each other, corresponding to each memory cell of the memory cell section. A read address generator comprising a plurality of D latches arranged in a line from the first to the last and inputting a common clock and supplying a Q output to each memory cell of the memory cell unit as a read signal; The common clock is input and the Q output of each D latch of the read address generator is D input, respectively, arranged in a line from the first to the last corresponding to each memory cell of the memory cell section. And a plurality of D latches for supplying a Q output to each memory cell of the memory cell section as a write signal. A dress generation unit, and a source of D input to each D latch of the read address generation unit, which is arranged in a line from a first number to a last number corresponding to each memory cell of the memory cell unit, and A selector unit comprising a plurality of selectors for selecting from the Q outputs of the plurality of D latches of the generation unit; and a plurality of D latches of the read address generation unit for supplying the Q output of the last D latch of the write address generation unit. And a selection control unit for selecting from the D input of the memory cell unit, wherein the selection control unit repeats the read / write operation of each memory cell of the memory cell unit only in the first to last direction in the first mode. The destination of the Q output of the last D latch of the write address generator is selected from the D inputs of the plurality of D latches of the read address generator. The read / write operation of each memory cell of the memory cell section at the time of loading is repeated in the first to last direction and the last to first direction alternately. Q of D latch
The output supply destination is set to a plurality of Ds of the read address generator.
Selecting from the D input of the latch, wherein each selector of the selector section repeats the read / write operation of each memory cell of the memory cell section in the first mode only in the first to last directions. A source of D input to each D latch of the read address generator is selected from Q outputs of the plurality of D latches of the write address generator, and reading of each memory cell of the memory cell unit is performed in the second mode. The source of the D input to each of the D latches of the read address generator is set to the write address generation so that the write operation is alternately repeated in the first to last direction and the last to first direction; A semiconductor delay device which is selected from Q outputs of a plurality of D latches of the section. 2. A memory cell unit comprising a plurality of memory cells arranged in a line from a first number to a last number and having a data input terminal and a data output terminal commonly connected to each other, corresponding to each memory cell of the memory cell unit. A read address generator comprising a plurality of D latches arranged in a line from the first to the last and inputting a common clock and supplying a Q output to each memory cell of the memory cell unit as a read signal; The common clock is input and the Q output of each D latch of the read address generator is D input, respectively, arranged in a line from the first to the last corresponding to each memory cell of the memory cell section. And a plurality of D latches for supplying a Q output to each memory cell of the memory cell section as a write signal. A dress generation unit, and a source of D input to each D latch of the read address generation unit, which is arranged in a line from a first number to a last number corresponding to each memory cell of the memory cell unit, and A selector unit comprising a plurality of selectors for selecting from the Q outputs of the plurality of D latches of the generation unit; and a plurality of D latches of the read address generation unit for supplying the Q output of the last D latch of the write address generation unit. A selection control unit for selecting from the D inputs of the memory cell unit in the first mode as a supply destination of the Q output of the last D latch of the write address generation unit. The read address is written via the first selector of the selector section so that the read / write operation of the cell is repeated only in the direction from the first to the last. The D input of the first D latch of the generation unit is selected, and in the second mode, the read / write operation of each memory cell in the memory cell unit is performed in the first to last direction and the last to first operation. And a state where the D input of the first D latch of the read address generation unit is selected via the first selector of the selector unit so as to alternately repeat in the direction of And switching the state of selecting the D input of the last D latch of the read address generation unit via the switch. The first selector of the selector unit switches the first D latch of the read address generation unit to the first D latch. As a source of the D input, the selection control unit is configured to repeat the read / write operation of each memory cell in the memory cell unit only in the first to last directions in the first mode. Q of to D latches of the last number of the write address generator
Output, and in the second mode, the read / write operation of each memory cell of the memory cell portion is alternately repeated in the first to last direction and the last to first direction, Switching between a state in which the Q output of the first D latch of the write address generator is selected and a state in which the Q output of the second D latch of the write address generator is selected; From the second to the last number before the last number of the read address generator, as the source of the D input to each of the D latches from the second to the last number before the last number. In the first mode, the first to last write address generators are arranged so that the read / write operation of each memory cell of the memory cell section is repeated only in the first to last directions. The Q outputs of the D latches of the respective numbers up to the previous number are respectively selected, and in the second mode, the read / write operation of each memory cell of the memory cell section is performed in the first to last directions and the last to second directions. A state in which the Q outputs of the D latches of the numbers from the first to the last two numbers before the last address of the write address generator are respectively selected so as to alternately repeat in the first direction and the write address generation section. And switching the state of selecting the Q output of each of the D latches of the numbers from the third to the last of the unit. The last selector of the selector unit switches the state to the last D latch of the read address generation unit. As a supply source of the D input, in the first mode, the write address is set so that the read / write operation of each memory cell of the memory cell portion is repeated only in the first to last directions. The Q output of the D latch of the number immediately before the last number of the dress generation unit is selected, and in the second mode, the read / write operation of each memory cell of the memory cell unit is performed in the direction from the first to the last number. A state in which the Q output of the D-latch of the number immediately before the last number of the write address generation unit is selected so as to alternately repeat from the last number to the first direction, and the write operation is performed via the selection control unit. A semiconductor delay device configured to switch between a state in which a Q output of a last D latch of an address generation unit is selected. 3. The first D-latch of the read address generator has a set input, and the second to last D-latches of the read address generator and the first D-latch of the write address generator. Each of the D latches from the first to the last has a reset input, and sets the first D latch of the read address generator at the time of start-up, and simultaneously sets each of the second to last D latches of the read address generator. 3. The semiconductor delay device according to claim 1, wherein the D latch of the number and the D latch of each number from the first to the last of the write address generator are reset.