JPH0798999A - Device for generating optional length data row - Google Patents

Abstract

PURPOSE:To generate an optional length data row in the case of reducing the number of the serial data generating at every output of the parallel data than the number of the parallel data by revising a frequency division ratio of a frequency division clock to the number of the serial data. CONSTITUTION:By a sequencer 1, a reference clock Fr is frequency divided by 16, and the frequency clock fx is supplied to an address generator 2, and the output of the data line is instructed to the generator 2. By the generator 2, an address is supplied to a storage position of a memory storing the data. Then, by the memories 31-3n, the data are outputted to a shift register 4, and by the register 4, a load signal is received to an LD terminal, and the data are fetched. The load signal is generated according to the clock fx also, and by the register 4, the data are outputted according to the clock Fr successively. By the register 4, after the data are fetched, the clock fx is received to the generator 2, and the address is supplied to the memories 31-3n. Then, by the memories, the data are outputted in parallel successively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data string generator, and more particularly to an arbitrary length data string generator capable of arbitrarily setting a data string length.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing an example of a waveform generator using a conventional data string generator. 1 is a sequencer for determining the output order of waveforms, 2 is an address generator controlled by the sequencer, 31-3n are a plurality of waveform memories for storing waveform data (digital data), 4 is parallel data converted to serial data The parallel-serial converter 5 is a digital-analog converter (DAC) that converts the digital waveform data output by the parallel-serial converter into an analog waveform signal. A sequence control circuit 6 controls the sequencer. At this time, if the serial data output of the parallel-serial converter 4 is used as it is, it is a data string generator.

Although high-speed operating DACs are relatively easy to obtain, it is generally difficult to operate a large capacity memory at high speed. Therefore, the digital data is divided and stored in a plurality of n waveform memories 31 to 3n, the data is read in parallel according to the low-speed divided clock fn, and parallel-serial conversion is performed by the parallel-serial converter 4 to serial data. , Parallel-serial converter 4 outputs serial data in accordance with a high-speed reference clock of frequency Fr. This makes it possible to generate an apparently high-speed data string. Address generator 2 corresponding to this
Are clocked by the divided clock fn and supply an address to each waveform memory. The divided clock fn is obtained by dividing the reference clock Fr by a dividing ratio n corresponding to the number n of memories.

[0004]

However, in the above-mentioned conventional example, serial data can be generated only in units of n corresponding to the number n of memories. That is, only a data string having an integral multiple of n can be generated, and a data string having an arbitrary length cannot be generated.

Therefore, an object of the present invention is to provide an arbitrary length data string generator capable of generating a data string of an arbitrary length at high speed. Another object of the present invention is to provide an arbitrary length data string generator having a relatively simple structure.

[0006]

Conventionally, in order to generate a data string at a speed higher than the operating speed of a memory, a data string generator has been constructed as follows. That is, digital
The data is divided and stored in a plurality of memories, a divided clock having a division ratio of the number of the plurality of memories is generated with respect to the reference clock, parallel data is output from the plurality of memories according to the divided clock, Each time parallel data is output, the parallel data is converted into serial data according to the reference clock to generate a data string.

However, in order to make the data string have an arbitrary length, it is necessary to reduce the number of serial data generated for each output of the parallel data in the process of generating the data string to be smaller than the number of parallel data. Therefore, the present invention changes the division ratio of the divided clock to the number of serial data in this case. As a result, unnecessary data included in the parallel data is discarded and a data string of arbitrary length can be generated.

[0008]

1 is a block diagram of a data string generator of the present invention. As compared with FIG. 4, the frequency division ratio of the frequency fx of the divided clock supplied from the sequencer 1 to the address generator 2 is not limited to the number of memories n and can be changed as necessary. A shift register is used as the parallel-serial converter 4. As described above, if the output of the parallel-serial converter 4 is converted into an analog signal by the digital-analog converter 5, it can be used as a waveform generator.

In the following description, the data string is the data string A
1 (or A2), the data string B, ... This control is done by the microprocessor in RAM
It can be realized by executing a program stored in a memory such as (random access memory). Note that FIG.
Then, these are shown as a sequence control circuit 6.
Further, the data string A1 (or A2) is a1, a2, ...
··· It is assumed to be composed of k pieces of data of a (k-2), a (k-1), and ak. k is an arbitrary integer. The number of memories is generally an arbitrary integer n, but here it is assumed that n = 16 for simplicity.

FIG. 2 is a timing diagram of the first embodiment of the present invention. In the figure, a is a reference clock, and b is a divided clock. C indicates a data string instructed by the sequencer 1 to the address generator 2. D indicates parallel data output from the memory. E is a load signal received by the shift register 4. In the first embodiment, if the number of data k of the data string A1 is divided by the number of memories n = 16, 14 is left. The sequencer 1 divides the reference clock Fr by 16 and divides the divided clock fx (division ratio 16) into the address generator 2
And the output of the data string A1 to the address generator 2. The address generator 2 supplies an address to a storage location of a memory that stores the data of the data string A1. Then, the memories 31 to 316 output the data a1 to a16 of the data string A1 in parallel to the shift register 4.
Next, the shift register 4 receives the load signal from the sequencer 1 at the LD terminal and fetches the data a1 to a16.
The load signal is also generated according to the divided clock. shift·
The register 4 sequentially outputs data from a1 according to the reference clock Fr. The shift register 4 stores data a1
After fetching a16, the address generator 2 receives the divided clock fx (frequency division ratio 16) and supplies the addresses to the memories 31 to 316. Then, the memory sequentially outputs the data after the data a17 in parallel in units of 16 data.

When the above operation is repeated and the end of the data of the data string A1 is approached, the remaining number of data becomes less than 16. That is, in the first embodiment, at the end of the data, a
Fourteen data items (k-13), ..., A (k-1), ak remain. Unwanted data * 1 and * 2 are stored in the remaining two of the 16 memories. Therefore, 14
16 pieces of data obtained by adding unnecessary data of * 1 and * 2 to this piece of data are fetched in parallel to the shift register 4.
Here, the divided clock fx has a division ratio of 16 to 14
Is changed to. Therefore, the last data a in the data string A1
When k is output from the shift register 4, the sequencer 1 outputs a load signal to the shift register 4, and the data b1 to b16 of the next data string B following the data string A1.
Is loaded. Therefore, unnecessary data * 1 and * 2 are
It is discarded without being output from the shift register 4.

In the first embodiment, the last remaining number of data is 1.
However, when the number of the remaining data is 1, for example, the sequencer 1 shifts the load signal by setting the division ratio of the divided clock fx to 1 when switching from the data sequence A1 to the data sequence B. It has to be supplied to the register 4. When the number of the remaining data is small as described above, the reading speed of the data from the memory may not catch up. Therefore, as a second embodiment of the present invention, a case where the remainder of dividing the data number k of the data string A2 by the memory number n is smaller than the predetermined remainder number j will be described.

FIG. 3 is a timing chart of the second embodiment. A, B, C, D and E are the same as in FIG. For the sake of simplicity, j is set to 4, and the number of data k of the data string A2 is divided by the number of memories n to leave 3 remainders. In addition, n =
16 will be described. Shift as in the first embodiment
When the data of the data string A2 is fetched into the register 4 in units of 16 data and the remaining data number is 19 (= 16 + 3) data, that is, a (k-18), ... A (k-18), ..., a
Eight data of (k-11) and unnecessary data of * 1 to * 8 are addressed. Then, the shift register 4 takes in 16 data in parallel, which is obtained by adding 8 data and 8 data * 1 to * 8. At this time, the division ratio of fx is changed from 16 to 8 according to the number of data to be output as serial data, which is 8. Subsequently, the address generator 2 receives fx (frequency division ratio 8) from the sequencer 1 and receives a (k-10), ...
An address is supplied to a memory for storing 11 pieces of data of ak and 5 pieces of data of * 9 to * 13, and a load signal is supplied to the shift register 4. Shift register 4
Takes in 16 pieces of data obtained by adding 5 pieces of unnecessary data * 9 to * 13 to 11 pieces of data. At this point, * 1 to * 8
Unnecessary data is discarded, and the division ratio of the divided clock fx is changed from 8 to 11. Subsequently, when the shift register 4 fetches the data b1 to b16 of the data string B with the divided clock fx (division ratio 11), unnecessary data * 9 to
* 13 is discarded. Thus the shift register 4
The data of the data string A2 is continuously output from a1 to the last ak according to the reference clock Fr.

As is apparent from the above description, in the second embodiment, the frequency division ratio does not become smaller than the integer j that can be set arbitrarily. Therefore, it suffices to set an appropriate j from the relationship between the operation speed of the memory and the speed of the reference clock Fr. Needless to say, if the remainder is zero when the number of data k is divided by the number of memories n, the data can be continuously output without changing the division ratio of the divided clock fx. Further, in the embodiment of the present invention, the division ratio is changed at the end of the data, but it may be changed at the beginning or the middle of the data string. That is, a place where the number of serial data generated for each output of parallel data is made smaller than the number of parallel data is provided at the beginning or in the middle of the data string, and at this time, the division ratio of the division clock is output in the parallel data. If the number of serial data to be changed is changed, the unnecessary data is discarded at the time when the shift register subsequently takes in the parallel data.

The number k of data in the data string can be set in advance by the operator as needed. Therefore, if the number n of memories is known, the remainder when the number k of data is divided by the number n of memories can be easily calculated. Further, even if data is taken in from the outside, it is easy to calculate the number of data, and it is easy for those skilled in the art to apply the present invention.

[0016]

According to the arbitrary length data string generator of the present invention, a plurality of memories output parallel data in accordance with a divided clock. At this time, when the number of serial data generated for each output of parallel data is made smaller than the number of parallel data, the division ratio of the divided clock is changed to the number of serial data. Therefore, even if there is unnecessary data in the parallel data, only the necessary data remains when the parallel data is converted into serial data. By appropriately controlling the divided clock in this way, it is possible to generate a data string of an arbitrary length without significantly changing the configuration and operation of the circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of an arbitrary length data string generator of the present invention.

FIG. 2 is a timing diagram of the first embodiment of the present invention.

FIG. 3 is a timing diagram of the second embodiment of the present invention.

FIG. 4 is a block diagram of a waveform generator using a conventional data string generator.

[Explanation of symbols]

 1 Sequencer 2 Address Generator 3 Memory 4 Parallel / Serial Converter 5 Digital / Analog Converter 6 Sequence Control Circuit

Claims (1)

[Claims] 1. Dividing digital data into a plurality of memories for storage, generating a divided clock with a dividing ratio of the number of the plurality of memories with respect to a reference clock, and generating the divided clocks according to the divided clocks. Output parallel data from the memory of
A data string generator for converting the parallel data into serial data according to the reference clock to generate a data string for each output of the parallel data, wherein the number of the serial data generated for each output of the parallel data is the parallel data. The arbitrary length data string generator is characterized in that the division ratio of the divided clock is changed to the number of the serial data when the number is smaller than the number of the serial data.