JP2544210B2 - Arbitrary waveform generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial field of application> The present invention stores defined waveform data in a waveform memory, sequentially reads the stored data, and performs analog conversion to define the defined waveform data. The present invention relates to an arbitrary waveform generator that generates a corresponding analog waveform, and more particularly, to a function capable of arbitrarily specifying the repetition and order of various defined waveforms.

<Prior Art> Conventionally, there is an arbitrary waveform generator of this type. An example thereof is shown in FIG. In the figure, 1 is a waveform memory in which waveform data is stored, and 2 is an address generator, which generates an address necessary for reading the waveform data from the waveform memory 1.

An arithmetic / control circuit 4 calculates the waveform data to be given to the waveform memory 1 by calculating the waveform definition formula, controls the address generator 2 to appropriately generate an address, and digital-analog converter (hereinafter referred to as DA conversion). Called a vessel)
A clock required for analog conversion is given to the circuit 3.

In such a configuration, the calculation / control circuit 4 calculates the waveform definition formula in advance to obtain the waveform data of the output waveform and stores it in the waveform memory 1. After that, the address is designated by the address generator 2, the waveform data is read from the waveform memory 1, and the DA converter 3 performs analog conversion. By repeating this data reading and analog conversion operation, an analog waveform corresponding to the waveform data stored in the waveform memory can be obtained.

Finally, the output waveform of this DA converter is further shaped into a smooth waveform through a low-pass filter, etc.
Since it is not directly related here, illustration and description thereof will be omitted.

With such an arbitrary waveform generator, an arbitrary waveform can be defined and an analog waveform corresponding thereto can be obtained.
It should be noted that several kinds of waveform data can be stored in advance in the waveform memory, and desired waveform data can be repeatedly output from among them by designating, or various waveform data can be output by appropriately changing the output order. Has become.

<Problems to be Solved by the Invention> However, in the conventional arbitrary waveform generator, when the output order of various waveforms is manually specified, the operation is complicated and the waveform output due to the switching operation is performed. However, there was a problem that the continuous output waveform could not be obtained.

In this case, needless to say, it is very convenient if the output order is automatically switched by the trigger input, and the waveform is continuously output without interruption during switching.

SUMMARY OF THE INVENTION An object of the present invention is to provide an arbitrary waveform generator which has been made in view of the above circumstances and which can sequentially switch a plurality of types of continuous repetitive waveforms by a trigger input.

<Means for Solving the Problems> According to the present invention for achieving such an object, defined waveform data is stored in a waveform memory,
An arbitrary waveform generator that generates analog waveforms corresponding to defined waveform data by sequentially reading the stored data and performing analog conversion, and calculates a plurality of types of waveform data to be stored in the waveform memory from defined equations. And the control / arithmetic circuit that generates and controls data and signals to be given to each part and stores the first and last addresses of the output waveform given by the control / arithmetic circuit when outputting multiple types of waveform data. Sequence storage means, an address storage means for setting a first address and a last address given by the sequence storage means, and an address generation means for generating an address to be given to the waveform memory when reading data from the waveform memory. Input from the control / arithmetic circuit The first address from the address storage means is set as an initial value at the rising edge of the first clock, and the address generation means outputs the address by incrementing the address according to the input clock, and outputs from the address generation means. Last address detecting means for comparing an address with the last address stored in the address storing means and outputting a coincidence signal which is also used as the load signal when they coincide with each other, and the last address after receiving a trigger from the outside. In synchronization with the coincidence signal from the address detecting means, a waveform switching signal necessary for storing the first address and the last address stored in the sequence storing means at the time when the trigger signal is input is sent to the address storing means. A waveform switching circuit for

<Operation> While the address generating means generates an address to be given to the waveform memory, the last address detecting means constantly monitors whether or not the address becomes the last address.

On the other hand, in the waveform switching circuit, when a trigger is input, a waveform switching signal for updating the first address fetched by the address generating means is generated in synchronization with the coincidence signal output from the last address detecting means after that.

As a result, new waveform data is switched and output.

<Examples> The present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an arbitrary waveform generator according to the present invention. In the figure, 1 is a waveform memory for storing various waveform data, 3 is a DA converter for converting the data output from the waveform memory 1 into analog data, and 4 is a plurality of types of waveform data stored in the waveform memory 1. Is a control / arithmetic circuit for generating and controlling data and signals to be given to each part, as well as being calculated by the definition formula.

Reference numeral 10 is a sequence storage means for storing the first address and last address of the output waveform given from the control / arithmetic circuit 4 when outputting a plurality of types of waveform data.

Reference numeral 20 is an address storage means in which the first address and the last address given from the sequence storage means 10 are set. As the address storage means, a normal register is used, and separate registers for the first address and the last address are used.

Reference numeral 30 is an address generating means for generating an address to be given to the waveform memory when reading data from the waveform memory 1. The first address of the address register 20 is used as an initial value,
The output address is incremented according to the clock given from the control / arithmetic circuit 4, and an up counter is normally used.

40 is a last address detecting means, and 30 is an address generating means.
It is to detect that the address output from is the last address, and a digital comparator is usually used. When the address output from the address generating means 30 matches the last address, a match signal is output, and the match signal is given to the address generating means 30 as a load signal (a signal for loading the first address). To be

Reference numeral 50 is a waveform switching circuit that generates a waveform switching signal for switching the output to another waveform while outputting a certain waveform.After receiving a trigger from the outside, the waveform currently being output is the last. When the address is reached, the waveform switching signal is output.

FIG. 2 shows a specific example of the waveform switching circuit 50, which has a configuration in which two stages of D-type flip-flops are connected. A high-level signal is always supplied to the D input terminal of the first-stage flip-flop 51, and when the trigger input is input, the output Q becomes high due to its rising. In the second-stage flip-flop 52, the Q output signal of the first-stage flip-flop is input to the D input terminal, and the coincidence signal from the last address detecting means 40 is introduced as a clock. The output Q of the second stage is used as a clear signal for the two flip-flops.

In such a waveform switching circuit, the Q output of the first-stage flip-flop becomes HIGH level by the trigger input, and the output Q of the second-stage flip-flop becomes HIGH when the coincidence signal is inputted thereafter. When the output Q of the second-stage flip-flop becomes HIGH, the two flip-flops are cleared at the same time and each output Q becomes LOW. However, there is a slight delay from the input of the clear signal until the output Q becomes LOW (the peculiar delay time width T _pd in the flip-flop).
_Therefore , the output Q of the second-stage flip-flop becomes a pulse signal having a pulse width T _pd . This pulse signal is used as a waveform switching signal.

The operation of such a configuration will be described below with reference to the time chart of FIG. In accordance with an instruction from the control / arithmetic circuit 4, the address storage means 20 has a sequence storage means.
The first address and the thrust address of the waveform (for example, waveform A) given from 10 are stored in advance. The address generating means 30 loads the first address of the waveform A and increments each time a clock is input.

The last address detecting means 40 monitors the output of the address generating means 30 and generates a coincidence signal (pulse signal) when it coincides with the last address.

This coincidence signal becomes a load signal of the address generating means 30, and when the clock from the control / arithmetic circuit 4 is input, the first address of the waveform A is set again in the address generating means 30.

As long as the values of the first address and the last address do not change, the address generating means 30 repeats this operation and repeatedly outputs the address for the waveform A. As a result, the waveform memory 1 sequentially outputs the data of the waveform A, and the DA converter 3 outputs the analog waveform corresponding to the waveform A. In this way, an infinite loop of the output waveform A is realized.

Now, during the output of the waveform A, if a trigger (an instruction to switch to the waveform B) is input [Fig. 3 (b)],
The waveform switching circuit 50 generates a waveform switching signal [(e) in FIG. 3] synchronized with the timing (rising edge) of the coincidence signal [(d) in FIG. 3] generated thereafter.

On the other hand, when the trigger is input, the first address and the last address of the waveform B are output to the sequence storage means 10 under the control of the control / arithmetic circuit 4. Therefore,
At the time when the waveform switching signal is generated, the first address and last address of the waveform B have already been output from the sequence storage means 10, and the contents of the address storage means 20 are changed to the first address and last address of the waveform B by the waveform switching signal. It is updated [(f) in FIG. 3].

The first address of the waveform B is synchronously loaded into the address generating means 30 (set at the rising edge of the first clock after the input of the load signal). After that, the waveform B is output according to the same operation as in the case of the infinite loop.

As described above, the waveform switching can be continuously performed.

The waveforms to be switched are not limited to the two types A and B, and a plurality of types of waveforms can be switched in an arbitrary order.

An application example of the present invention will be described below. For example, in a waveform read from a disk, a read error may occur due to a change in peak value. In such applications, the peak value is gradually increased or decreased,
You need to look at the value where the read error begins to occur.
If the waveform switching function of the arbitrary waveform generator of the present invention is used, several types of waveforms having different peak values are prepared as shown in FIG. 4, and these waveforms are appropriately switched by trigger input to generate. The waveform at which the read error starts to occur can be examined, and the peak value of the waveform can be easily obtained.

<Effects of the Invention> As described in detail above, according to the present invention, by providing a waveform switching circuit that generates a waveform switching signal at the timing of waveform switching after a trigger is input, a plurality of types of waveforms can be input as a trigger. Thus, it is possible to automatically and sequentially switch the waveforms, and it is possible to continuously output the waveforms without interrupting the waveform output.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an arbitrary waveform generator according to the present invention, FIG. 2 is a specific example of a waveform switching circuit, FIG. 3 is a time chart for explaining the operation, and FIG. FIG. 5 is a diagram showing an example of an output waveform, and FIG. 5 is a configuration diagram showing an example of a conventional arbitrary waveform generator. 1 ... Waveform memory, 3 ... DA converter, 4 ... Control / arithmetic circuit, 10 ... Sequence storage means, 20 ... Address storage means, 30 ... Address generation means, 40 ... Last address detection means, 50: Waveform switching circuit.

Claims (1)

(57) [Claims] 1. An arbitrary waveform generator for storing defined waveform data in a waveform memory, sequentially reading the stored data, and performing analog conversion to generate an analog waveform corresponding to the defined waveform data. When a plurality of types of waveform data to be stored in the waveform memory are calculated by a definition formula, and a control / arithmetic circuit for generating and controlling data and signals to be supplied to each part and a plurality of types of waveform data are output. Sequence storing means for storing a first address and a last address of an output waveform given by the control arithmetic circuit, an address storing means for setting a first address and a last address given by the sequence storing means, and data from the waveform memory. Generates an address to be given to the waveform memory when reading Therefore, the first address from the address storage means is set as an initial value at the rising edge of the first clock input from the control / arithmetic circuit after the load signal is given, and the address is incremented according to the input clock. And the address output means for outputting the same, and compares the address output from the address generating means with the last address stored in the address storage means, and outputs a match signal which is also used as the load signal when they match. After receiving a trigger from the address detection means and the outside, the first address and the last address stored in the sequence storage means at the time when the trigger signal is input are synchronized with the coincidence signal from the last address detection means. Waves required to store in the address storage means Arbitrary waveform generator, characterized in that comprises a waveform switching circuit for sending a switching signal, and can be output by switching a plurality of types of waveform automatically.