JP3249671B2 - Arbitrary length data string generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data string generator, and more particularly to an arbitrary-length data string generator capable of arbitrarily setting the length of a data string.

[0002]

2. Description of the Related Art Data stream generators are used to provide a desired digital pattern to various digital electronic devices. For example, during the development of various devices, a signal to be output from a circuit that is not yet completed is generated by the data string generator, and is used to check other circuits.

FIG. 3 is a block diagram showing an example of a conventional data string generator. Reference numeral 2 denotes a sequencer for determining the output order of parallel data. Reference numeral 1 denotes a sequence control circuit that controls the sequencer 2. Reference numeral 3 denotes an address generator controlled by a sequencer, 4 denotes a memory for storing parallel data, and 5 denotes a parallel / serial converter (SR such as a shift register) for converting parallel data into serial data. Serial data can be used as is as described above, but multiple serial data generated in the same
If the signal is converted into an analog signal using an analog converter (D / A), it can be applied as an analog waveform generator.

Although high-speed D / A is relatively easy to obtain, it is generally difficult to operate a large-capacity memory at high speed. Therefore, the parallel data of the bit number n is stored in the memory 4 , the data is read out in parallel according to the low-speed frequency-divided clock (frequency fn), and the parallel / serial converter 5 converts the data into parallel data. The serial data is output from the parallel-to-serial converter 5 according to a high-speed reference clock. Thereby, an apparently high-speed data string can be generated. In response, the address generator 3 is clocked by the divided clock fn and supplies an address to the memory 4 .
Note that the divided clock fn is obtained by dividing the reference clock fr by the dividing ratio n in accordance with the number n of bits of the parallel data.

[0005]

However, in the above-mentioned conventional example, serial data can be generated only in units of n units corresponding to the bit number n of the parallel data output from the memory. That is, only a data string having a length that is an integral multiple of n can be generated, and a data string having an arbitrary length cannot be generated. Further, when an operation such as jump or loop (repetition) is performed when the next address of the memory is specified, it is necessary to add a complicated circuit to the sequencer.

An object of the present invention is to provide an arbitrary-length data string generator capable of generating a data string of an arbitrary length at high speed. It is another object of the present invention to provide an arbitrary-length data string generator having a relatively simple configuration.

[0007]

SUMMARY OF THE INVENTION The present invention provides an arbitrary-length data string generator capable of generating a high-speed data string of an arbitrary length. The first memory 12 has n
It stores bit parallel data. n is an integer of 2 or more. The first parallel-serial conversion means 14 loads parallel data according to a load signal, performs parallel-serial conversion, and outputs it as serial data according to a clock. The second memory 22 includes:
It stores n-bit parallel load control data, which is provided corresponding to each of the parallel data. The k-bit (k is a preset integer of n or less) bits generated from the corresponding parallel data is stored. According to the length of serial data,
The k-th bit is data indicating the load. The second parallel / serial conversion means 24 loads the load control data according to the load signal, performs parallel / serial conversion, and outputs it as a load signal according to the clock. Address supply means 10
Supplies addresses of the first and second memories for storing parallel data and load control data corresponding thereto.

At this time, the first parallel / serial conversion means 14 loads the parallel data according to the load signal output from the second parallel / serial conversion means 24, and then loads the next parallel data at the k-th clock. Thereby, the length of serial data generated from one parallel data is controlled, and as a result, a data string of any length not limited to a multiple of the number of bits of the parallel data can be stored regardless of the low operation speed of the memory. In accordance with the high operating speed of the parallel / serial conversion means.

[0009]

FIG. 1 is a block diagram showing a preferred embodiment of a data string generating apparatus according to the present invention. Memory (first memory) 12
In each address, n-bit parallel data is stored. n is an integer of 2 or more. The first shift register (SR) 14 is a parallel-serial conversion unit that loads parallel data from the memory 12 and converts the parallel data into serial data. Second
The memory (load control memory) 22 stores n-bit load control data in which an arbitrary predetermined bit indicates a load. The second shift register (SR) 24 is a parallel / serial conversion unit that loads the load control data and converts it into a load signal. The address generator 10 supplies a common address to the memory 12 and the load control memory 22. The output of the shift register 14 is converted to a digital-to-analog converter (D
As described above, if an analog signal is converted using / A) or the like, it can be used as a waveform generator. As is well known, the loop 16 is provided for executing a jump instruction for skipping an intermediate address and specifying a next address. Operations such as reading and writing of data in each memory are controlled by a central processing unit (CPU, not shown).

The number n of bits of the parallel data is an arbitrary integer of 2 or more as described above. However, in the following description, n = 16 for simplicity. That is, each address of the first and second memories has 16-bit data (parallel data).
Is stored. Therefore, in this case, the number of bits of each parallel data when the parallel data is loaded from the first and second memories into the first and second shift registers is always 16 bits.

FIG. 2 is a timing chart for the serial data output from the first shift register 14 and the clock (CLK) of the load signal output from the second shift register 24. The serial data A has 16 data. At this time, the serial data A is stored in the first shift register 1
4 is simultaneously loaded with the second shift register 2
The load control data A loaded into No. 4 has data indicating the load in the 16th bit. Therefore, the load signal rises at the 16th clock after the load is performed first. Each shift register receives this load signal and loads parallel data from the corresponding memory. That is, the load signal determines the load timing.

Similarly, the load control data B corresponding to the serial data B has data indicating a load in the ninth bit. Therefore, the load signal rises at the ninth clock after the load is performed first. Similarly, the length of serial data generated from one piece of parallel data can be adjusted within a range of n or less by inserting data indicating load into an arbitrary bit of the n-bit load control data. Therefore, a data string having an arbitrary length can be generated by combining serial data generated from one piece of parallel data. In the load control data, data indicating the load among the n bits is set to, for example, “1”, and the other data is set to “
0 "may be set.

Although the embodiment of FIG. 1 shows a case in which only one first memory stores parallel data, a plurality of memories may be used. According to this, parallel data having a larger number of bits can be called from the first memory to generate long serial data at a time. In this case, the configuration is such that parallel data (load control data) having the same number of bits as the above parallel data is stored in each address of the second memory (load control memory). As a result, even if the next specified address jumps, the contents of each address in the first memory and the second memory always correspond, and the length of serial data generated from one parallel data is set to a preset length. I can do it.

[0014]

Conventionally, in order to compensate for the low-speed operation of a large-capacity memory, parallel data output from a memory is loaded into parallel-serial conversion means and converted into serial data. In the data string generating apparatus, in particular, by controlling the timing of loading parallel data to the parallel / serial conversion means, the serial data output from the parallel / serial conversion means can be converted to an arbitrary length including a short data string equal to or less than the bit number of the parallel data. I can do it. Therefore, the operation speed of the memory may be relatively low as before, while the output serial data can be made high speed because of the clock speed of the parallel / serial conversion means.

[Brief description of the drawings]

FIG. 1 is a block diagram of a preferred embodiment of an arbitrary-length data string generator according to the present invention.

FIG. 2 is a timing chart of serial data and a load signal.

FIG. 3 is a block diagram of an example of a conventional data string generator.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Address supply means 12 1st memory 14 1st parallel-serial conversion means 22 2nd memory (load control memory) 24 2nd parallel-serial conversion means

Claims (1)

(57) [Claims] A first memory for storing n-bit parallel data; a first parallel / serial conversion means for loading the parallel data to perform parallel / serial conversion, and outputting the data as serial data in accordance with a clock; Corresponding to the length of the serial data of k bits (k is a preset integer of n or less) generated from the corresponding parallel data,
a second memory for storing n-bit parallel load control data in which a k-th bit indicates a load; a second parallel-serial conversion for loading the load control data to perform parallel-serial conversion and outputting as a load signal in accordance with the clock Means, and address supply means for supplying addresses of the first and second memories for storing the parallel data and the load control data corresponding thereto, and after loading the parallel data according to the load signal, An arbitrary-length data sequence, wherein the next parallel data is loaded into the first parallel-serial conversion means at the k-th clock, and the corresponding load control data is loaded into the second parallel-serial conversion means. Generator.